netdev - Re: [net-next 10/15] net/mlx5e: Let channels be SD-aware

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Message-ID: <effce034-6bc5-4e98-9b21-c80e8d56f705@nvidia.com>
Date: Mon, 8 Jan 2024 14:30:54 +0200
From: Gal Pressman <gal@...dia.com>
To: Jakub Kicinski <kuba@...nel.org>, Saeed Mahameed <saeed@...nel.org>
Cc: "David S. Miller" <davem@...emloft.net>, Paolo Abeni <pabeni@...hat.com>,
 Eric Dumazet <edumazet@...gle.com>, Saeed Mahameed <saeedm@...dia.com>,
 netdev@...r.kernel.org, Tariq Toukan <tariqt@...dia.com>
Subject: Re: [net-next 10/15] net/mlx5e: Let channels be SD-aware

On 05/01/2024 0:50, Jakub Kicinski wrote:
> On Wed, 20 Dec 2023 16:57:16 -0800 Saeed Mahameed wrote:
>> Example for 2 mdevs and 6 channels:
>> +-------+---------+
>> | ch ix | mdev ix |
>> +-------+---------+
>> |   0   |    0    |
>> |   1   |    1    |
>> |   2   |    0    |
>> |   3   |    1    |
>> |   4   |    0    |
>> |   5   |    1    |
>> +-------+---------+
> 
> Meaning Rx queue 0 goes to PF 0, Rx queue 1 goes to PF 1, etc.?

Correct.

> Is the user then expected to magic pixie dust the XPS or some such
> to get to the right queue?

I'm confused, how are RX queues related to XPS?
XPS shouldn't be affected, we just make sure that whatever queue XPS
chose will go out through the "right" PF.

So for example, XPS will choose a queue according to the CPU, and the
driver will make sure that packets transmitted from this SQ are going
out through the PF closer to that NUMA.

> 
> How is this going to get represented in the recently merged Netlink
> queue API?

Can you share a link please?

All the logic is internal to the driver, so I expect it to be fine, but
I'd like to double check.