netdev - Re: [PATCH 3/6] arm64: dts: qcom: ipq5332: Add MDIO device tree

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Message-ID: <73b3b6c5-5196-49fd-8e42-cc2d3dfbd30c@quicinc.com>
Date: Fri, 12 Jan 2024 23:58:30 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Andrew Lunn <andrew@...n.ch>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_suruchia@...cinc.com>,
        <quic_soni@...cinc.com>, <quic_pavir@...cinc.com>,
        <quic_souravp@...cinc.com>, <quic_linchen@...cinc.com>,
        <quic_leiwei@...cinc.com>
Subject: Re: [PATCH 3/6] arm64: dts: qcom: ipq5332: Add MDIO device tree



On 1/12/2024 12:13 AM, Dmitry Baryshkov wrote:
> On Thu, 11 Jan 2024 at 18:00, Jie Luo <quic_luoj@...cinc.com> wrote:
>>
>>
>>
>> On 1/10/2024 9:35 PM, Andrew Lunn wrote:
>>> On Wed, Jan 10, 2024 at 07:20:56PM +0800, Luo Jie wrote:
>>>> Add the MDIO device tree of ipq5332.
>>>>
>>>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/ipq5332.dtsi | 44 +++++++++++++++++++++++++++
>>>>    1 file changed, 44 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> index bc89480820cb..e6c780e69d6e 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>>> @@ -214,6 +214,38 @@ serial_0_pins: serial0-state {
>>>>                               drive-strength = <8>;
>>>>                               bias-pull-up;
>>>>                       };
>>>> +
>>>> +                    mdio0_pins: mdio0-state {
>>>> +                            mux_0 {
>>>> +                                    pins = "gpio25";
>>>> +                                    function = "mdc0";
>>>> +                                    drive-strength = <8>;
>>>> +                                    bias-disable;
>>>> +                            };
>>>> +
>>>> +                            mux_1 {
>>>> +                                    pins = "gpio26";
>>>> +                                    function = "mdio0";
>>>> +                                    drive-strength = <8>;
>>>> +                                    bias-pull-up;
>>>> +                            };
>>>> +                    };
>>>> +
>>>> +                    mdio1_pins: mdio1-state {
>>>> +                            mux_0 {
>>>> +                                    pins = "gpio27";
>>>> +                                    function = "mdc1";
>>>> +                                    drive-strength = <8>;
>>>> +                                    bias-disable;
>>>> +                            };
>>>> +
>>>> +                            mux_1 {
>>>> +                                    pins = "gpio28";
>>>> +                                    function = "mdio1";
>>>> +                                    drive-strength = <8>;
>>>> +                                    bias-pull-up;
>>>> +                            };
>>>
>>> I don't know why i'm asking this, because i don't really expect a
>>> usable answer. What sort of MUX is this? Should you be using one of
>>> the muxes in drivers/net/mdio/mdio-mux-* or something similar?
>>>
>>>       Andrew
>>
>> Sorry for the confusion, the pin nodes are for the MDIO and MDC, these
>> PINs are used by the dedicated hardware MDIO block in the SoC. I will
>> update the node name from mux_0 to MDC, mux_1 to MDIO, to make it clear.
>> The driver for this node is drivers/net/mdio/mdio-ipq4019.c, it is not
>> related to the mdio-mux-* code.
> 
> Have you read Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
> ? Have you validated your DTSI files against DT schema? How many
> warnings will you observe if you rename the mux_0 node to MDC?
> 
Sorry for this error, we will follow the DTSI validation process and 
update the patch with the right updates after validation, when the patch 
series resumes.

Thanks for correction and the pointer to the tlmm YAML file.