lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <82534d84-0acf-4ada-9a65-4e5089dff890@lunn.ch>
Date: Mon, 15 Jan 2024 23:37:32 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Jiawen Wu <jiawenwu@...stnetic.com>
Cc: davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, linux@...linux.org.uk, horms@...nel.org,
	netdev@...r.kernel.org, mengyuanlou@...-swift.com
Subject: Re: [RFC PATCH net-next] net: txgbe: use irq_domain for interrupt
 controller

On Mon, Jan 15, 2024 at 05:16:21PM +0800, Jiawen Wu wrote:
> Use irq_domain infrastructure for MAC interrupt controller, which above
> the GPIO interrupt controller.

What is missing from this description is an answer to the question
Why?

> +static void txgbe_misc_irq_mask(struct irq_data *d)
> +{
> +}
> +
> +static void txgbe_misc_irq_unmask(struct irq_data *d)
> +{
> +	struct txgbe *txgbe = irq_data_get_irq_chip_data(d);
> +	struct wx *wx = txgbe->wx;
> +
> +	wx_intr_enable(wx, TXGBE_INTR_MISC);
> +}

This looks odd. You can unmask an interrupt, but you cannot mask it?
Also, typically, an interrupt chip has multiple interrupt sources. d
points to one source. You typically need to look at d->hwirq to
determine which interrupt should be masked/unmasked.

	Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ