netdev - Re: (subset) [PATCH v2 0/7] MPFS clock fixes required for correct CAN clock modeling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20240206-cloud-subduing-cb42cc496621@spud>
Date: Tue,  6 Feb 2024 14:27:31 +0000
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org,
	Conor Dooley <conor@...nel.org>
Cc: Conor Dooley <conor.dooley@...rochip.com>,
	Daire McNamara <daire.mcnamara@...rochip.com>,
	Wolfgang Grandegger <wg@...ndegger.com>,
	Marc Kleine-Budde <mkl@...gutronix.de>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	linux-can@...r.kernel.org,
	netdev@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-clk@...r.kernel.org
Subject: Re: (subset) [PATCH v2 0/7] MPFS clock fixes required for correct CAN clock modeling

From: Conor Dooley <conor.dooley@...rochip.com>

On Mon, 22 Jan 2024 12:19:48 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> While reviewing a CAN driver internally for MPFS [1], I realised
> that the modeling of the MSSPLL such that only one of its outputs could
> be used was not correct. The CAN controllers on MPFS take 2 input
> clocks - one that is the bus clock, acquired from the main MSSPLL and
> a second clock for the AHB interface to the result of the SoC.
> Currently the binding for the CAN controllers and the represetnation
> of the MSSPLL only allows for one of these clocks.
> Modify the binding and devicetree to expect two clocks and rework the
> main clock controller driver for MPFS such that it is capable of
> providing multiple outputs from the MSSPLL.
> 
> [...]

And this one is applied to riscv-dt-for-next. I don't think sending this
for the -rcs is needed as there's no impact until the CAN driver shows up.

[7/7] riscv: dts: microchip: add missing CAN bus clocks
      https://git.kernel.org/conor/c/6c7353836a91

Thanks,
Conor.