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Date: Fri, 16 Feb 2024 18:02:03 +0800
From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@...nel.org>
To: Yisen Zhuang <yisen.zhuang@...wei.com>,
Salil Mehta <salil.mehta@...wei.com>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Yang Xiwen <forbidden405@...mail.com>,
Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Yang Xiwen <forbidden405@...look.com>
Subject: [PATCH v2 4/6] dt-bindings: net: add hisilicon,hisi-femac
From: Yang Xiwen <forbidden405@...look.com>
This binding gets rewritten. Compared to previous txt based binding doc,
the following changes are made according to the TRM:
- No "hisi-femac-v1/2" binding anymore
- Remove unmaintained Hi3516 SoC, add Hi3798MV200
- add MDIO subnode
- add ahb bus clock, phy clock and reset
Signed-off-by: Yang Xiwen <forbidden405@...look.com>
---
.../bindings/net/hisilicon,hisi-femac.yaml | 117 +++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml
new file mode 100644
index 000000000000..08158118c9c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon,hisi-femac.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/hisilicon,hisi-femac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Fast Ethernet MAC controller
+
+maintainers:
+ - Yang Xiwen <forbidden405@...mail.com>
+
+allOf:
+ - $ref: ethernet-controller.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - hisilicon,hi3798mv200-femac
+ - const: hisilicon,hisi-femac
+
+ reg:
+ items:
+ - description: The first region is the MAC core register base and size.
+ - description: The second region is the global MAC control register.
+
+ ranges:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: mac
+ - const: macif
+ - const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: mac
+ - const: phy
+
+ hisilicon,phy-reset-delays-us:
+ items:
+ - description: The 1st cell is reset pre-delay in micro seconds.
+ - description: The 2nd cell is reset pulse in micro seconds.
+ - description: The 3rd cell is reset post-delay in micro seconds.
+
+patternProperties:
+ '^mdio@[0-9a-f]+$':
+ $ref: hisilicon,hisi-femac-mdio.yaml#
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - phy-connection-type
+ - phy-handle
+ - hisilicon,phy-reset-delays-us
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/histb-clock.h>
+
+ ethernet@...0000 {
+ compatible = "hisilicon,hi3798mv200-femac", "hisilicon,hisi-femac";
+ reg = <0x9c30000 0x1000>, <0x9c31300 0x200>;
+ ranges = <0x0 0x9c30000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_ETH0_MAC_CLK>,
+ <&crg HISTB_ETH0_MACIF_CLK>,
+ <&crg 62>;
+ clock-names = "mac", "macif", "phy";
+ resets = <&crg 0xd0 3>, <&crg 0x388 4>;
+ reset-names = "mac", "phy";
+ phy-handle = <&fephy>;
+ phy-connection-type = "mii";
+ // To be filled by bootloader
+ mac-address = [00 00 00 00 00 00];
+ hisilicon,phy-reset-delays-us = <10000 10000 500000>;
+ status = "okay";
+
+ mdio@...0 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x1100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+ };
--
2.43.0
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