netdev - Re: [PATCH 1/6] net: hisilicon: add support for hisi

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Message-ID:
 <SEZPR06MB69593E00C6A69AFAC61BF2BD964C2@SEZPR06MB6959.apcprd06.prod.outlook.com>
Date: Fri, 16 Feb 2024 21:41:29 +0800
From: Yang Xiwen <forbidden405@...look.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yisen Zhuang <yisen.zhuang@...wei.com>,
 Salil Mehta <salil.mehta@...wei.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Yang Xiwen <forbidden405@...mail.com>,
 Heiner Kallweit <hkallweit1@...il.com>, Russell King
 <linux@...linux.org.uk>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 1/6] net: hisilicon: add support for hisi_femac core on
 Hi3798MV200

On 2/16/2024 9:23 PM, Andrew Lunn wrote:
>> +	// Register the optional MDIO bus
>> +	for_each_available_child_of_node(node, mdio_np) {
>> +		if (of_node_name_prefix(mdio_np, "mdio")) {
>> +			priv->mdio_pdev = of_platform_device_create(mdio_np, NULL, dev);
>> +			of_node_put(mdio_np);
>> +			if (!priv->mdio_pdev) {
>> +				dev_err(dev, "failed to register MDIO bus device\n");
>> +				goto out_free_netdev;
>> +			}
>> +			mdio_registered = true;
>> +			break;
>> +		}
>> +	}
>> +
>> +	if (!mdio_registered)
>> +		dev_warn(dev, "MDIO subnode notfound. This is usually a bug.\n");
> I don't understand the architecture of this device yet...
>
> It seems like you have an integrated PHY? In the example, you used a
> phy-handle to bind the MAC to the PHY. So why is the MDIO bus
> optional?
Because the MAC can also support external PHY according to the 
datasheet. Maybe some other SoCs didn't implement this internal PHY and 
used an external PHY instead.
>
> Do the MII signals from the MAC also go to SoC pins, so you could use
> an external PHY? Is there a SERDES so you could connect to an SFP
> cage?
No. MII signals is not accessible outside of the SoC. The SoC only 
exports FEPHY pins (i.e. RXN(P) and TXN(P)).
>
> Also, do the MDIO pins go to SoC pins? Can the MDIO bus master be used
> to control external PHYs?
It can, but not for Hi3798MV200. The datasheet said it can use both 
internal phy or external phy. But for Hi3798MV200, seems impossible.
>
> If everything is internal, fixed in silicon, no variation possible,
> you don't need to describe the MDIO bus in DT. The MAC driver can
> register it, and then get the PHY at the hard coded address it uses.
>
> 	 Andrew

-- 
Regards,
Yang Xiwen