netdev - Re: [PATCH 1/6] net: hisilicon: add support for hisi

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Message-ID:
 <SEZPR06MB695985C02333DC5915A1203E964C2@SEZPR06MB6959.apcprd06.prod.outlook.com>
Date: Fri, 16 Feb 2024 22:08:34 +0800
From: Yang Xiwen <forbidden405@...look.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yisen Zhuang <yisen.zhuang@...wei.com>,
 Salil Mehta <salil.mehta@...wei.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Yang Xiwen <forbidden405@...mail.com>,
 Heiner Kallweit <hkallweit1@...il.com>, Russell King
 <linux@...linux.org.uk>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 1/6] net: hisilicon: add support for hisi_femac core on
 Hi3798MV200

On 2/16/2024 9:58 PM, Andrew Lunn wrote:
> On Fri, Feb 16, 2024 at 09:41:29PM +0800, Yang Xiwen wrote:
>> On 2/16/2024 9:23 PM, Andrew Lunn wrote:
>>>> +	// Register the optional MDIO bus
>>>> +	for_each_available_child_of_node(node, mdio_np) {
>>>> +		if (of_node_name_prefix(mdio_np, "mdio")) {
>>>> +			priv->mdio_pdev = of_platform_device_create(mdio_np, NULL, dev);
>>>> +			of_node_put(mdio_np);
>>>> +			if (!priv->mdio_pdev) {
>>>> +				dev_err(dev, "failed to register MDIO bus device\n");
>>>> +				goto out_free_netdev;
>>>> +			}
>>>> +			mdio_registered = true;
>>>> +			break;
>>>> +		}
>>>> +	}
>>>> +
>>>> +	if (!mdio_registered)
>>>> +		dev_warn(dev, "MDIO subnode notfound. This is usually a bug.\n");
>>> I don't understand the architecture of this device yet...
>>>
>>> It seems like you have an integrated PHY? In the example, you used a
>>> phy-handle to bind the MAC to the PHY. So why is the MDIO bus
>>> optional?
>> Because the MAC can also support external PHY according to the datasheet.
>> Maybe some other SoCs didn't implement this internal PHY and used an
>> external PHY instead.
>>> Do the MII signals from the MAC also go to SoC pins, so you could use
>>> an external PHY? Is there a SERDES so you could connect to an SFP
>>> cage?
>> No. MII signals is not accessible outside of the SoC. The SoC only exports
>> FEPHY pins (i.e. RXN(P) and TXN(P)).
>>> Also, do the MDIO pins go to SoC pins? Can the MDIO bus master be used
>>> to control external PHYs?
>> It can, but not for Hi3798MV200. The datasheet said it can use both internal
>> phy or external phy. But for Hi3798MV200, seems impossible.
> So for the Hi3798MV200 this is not optional, the MDIO bus is
> mandatory.
>
> Also, it sounds like it exists in the silicon. So it is better to
> always describe it in the .dtsi file.
>
> And i took a quick look at mdio-hisi-femac.c. It has a probe function
> which does:
>
>          data->membase = devm_platform_ioremap_resource(pdev, 0);
>
> meaning it expects to have its own address range. It is a device of
> its own. That also explains the compatible. So please move the MDIO
> bus to a node of its own, rather than embedding it within the MAC
> node.

It won't work. Hi3798MV200 does not have a dedicated MDIO bus clock. 
this clock is merged to MAC clock for this SoC. We need to enable 
CLK_BUS and CLK_MAC before MDIO bus access.

Assigning CLK_MAC and CLK_BUS to MDIO bus device does not work either. 
Because the clocks will be enabled twice, the MAC controller will be 
unable to disable the clocks during PHY reset.

Note that the source is contributed by HiSilicon almost 8 yrs ago. And 
they had never proved that this driver  works. They are not doing things 
like this in downstream.

>
> 	Andrew

-- 
Regards,
Yang Xiwen