netdev - Re: [PATCH 4/6] dt-bindings: net: add hisilicon-femac

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <SEZPR06MB6959CC3284F21DB82856891D964C2@SEZPR06MB6959.apcprd06.prod.outlook.com>
Date: Fri, 16 Feb 2024 08:20:50 +0800
From: Yang Xiwen <forbidden405@...look.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yisen Zhuang <yisen.zhuang@...wei.com>,
 Salil Mehta <salil.mehta@...wei.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Yang Xiwen <forbidden405@...mail.com>,
 Heiner Kallweit <hkallweit1@...il.com>, Russell King
 <linux@...linux.org.uk>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 4/6] dt-bindings: net: add hisilicon-femac

On 2/16/2024 8:06 AM, Andrew Lunn wrote:
>> +  clocks:
>> +    minItems: 3
>> +    maxItems: 3
>> +
>> +  clock-names:
>> +    items:
>> +      - const: mac
>> +      - const: macif
>> +      - const: phy
> The C code has:
>
> +enum clk_type {
> +       CLK_MAC,
> +       CLK_BUS,
> +       CLK_PHY,
> +       CLK_NUM,
> +};
>
> Could you explain BUS vs macif?
To be honest, I don't know. "macif" is used by hisi-gmac driver, but in 
the TRM it's called "bus". So I guess it's just an alias? As you 
mentioned, I'll stick to macif everywhere, to keep sync with hisi-gmac 
driver.
>
> Also, what exactly is the PHY clock?
As the name suggests, it's not part of the mac controller actually, 
rather it's the clock of the internal PHY. The SoC (or the PHY/MAC, I 
don't know exactly which) is quirky that it is mandatory to disable PHY 
CLK before MAC reset or else the PHY won't work(see 
hisi_femac_phy_reset()). I can't find a better solution. Letting the 
ethernet controller manage all clocks and resets seems the easiest way 
to handle this quirk.
>
>        Andrew

-- 
Regards,
Yang Xiwen