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Message-ID: <ZdDLI4o1Bll1xvH6@hoboy.vegasvil.org>
Date: Sat, 17 Feb 2024 07:05:07 -0800
From: Richard Cochran <richardcochran@...il.com>
To: Vinicius Costa Gomes <vinicius.gomes@...el.com>
Cc: intel-wired-lan@...ts.osuosl.org, sasha.neftin@...el.com,
kurt@...utronix.de, anthony.l.nguyen@...el.com,
jesse.brandeburg@...el.com, "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Jeff Kirsher <jeffrey.t.kirsher@...el.com>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [iwl-net v1 2/2] igb: Fix missing time sync events
On Fri, Feb 16, 2024 at 05:04:54PM -0800, Vinicius Costa Gomes wrote:
> Fix "double" clearing of interrupts, which can cause external events
> or timestamps to be missed.
>
> The E1000_TSIRC Time Sync Interrupt Cause register can be cleared in two
> ways, by either reading it or by writing '1' into the specific cause
> bit. This is documented in section 8.16.1.
That is not what the doc says.
It says this:
Note: Once ICR.Time_Sync is set, the internal value of this
register should be cleared by writing 1b to *all* bits
or cleared by a read to enable receiving an additional
ICR.Time_Sync interrupt.
- IntelĀ® Ethernet Controller I210 Datasheet,
Revision Number: 3.1, June 2017, page 469
It says *all* bits. This implies that the interrupt sources may be
cleared individually. Because the non-acked bits are still pending,
the level interrupt should still be active, and the "missing" event
will be handled at the next invocation of the handler.
> The following flow was used:
> 1. read E1000_TSIRC into 'tsicr';
> 2. handle the interrupts present into 'tsirc' and mark them in 'ack';
> 3. write 'ack' into E1000_TSICR;
>
> As both (1) and (3) will clear the interrupt cause, if an interrupt
> happens between (1) and (3) it will be ignored, causing events to be
> missed.
Are you sure?
Does setting ICR.Time_Sync[TXTS] also clear ICR.Time_Sync[RXTS] ?
That is what you seem to be saying.
Thanks,
Richard
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