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Message-ID: <6bb634fb-fe02-085b-a96f-ea56698ebcb4@bootlin.com>
Date: Mon, 19 Feb 2024 11:40:56 +0100 (CET)
From: Romain Gantois <romain.gantois@...tlin.com>
To: Piotr Wejman <piotrwejman90@...il.com>
cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>, "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>, netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] net: stmmac: fix rx queue priority assignment
Hello Piotr,
On Mon, 19 Feb 2024, Piotr Wejman wrote:
> static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
> - u32 prio, u32 queue)
> + u32 prio_mask, u32 queue)
> {
> void __iomem *ioaddr = hw->pcsr;
> - u32 base_register;
> - u32 value;
> + u32 clear_mask = 0;
> + u32 ctrl2, ctrl3;
> + int i;
>
> - base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
> - if (queue >= 4)
> - queue -= 4;
> + ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
> + ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
>
> - value = readl(ioaddr + base_register);
> + for (i = 0; i < 4; i++)
> + clear_mask |= ((prio_mask << GMAC_RXQCTRL_PSRQX_SHIFT(i)) &
> + GMAC_RXQCTRL_PSRQX_MASK(i));
>
> - value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
> - value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
> + ctrl2 &= ~clear_mask;
> + ctrl3 &= ~clear_mask;
> +
> + if (queue < 4) {
> + ctrl2 |= (prio_mask << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
This is a bit of a nitpick but do you think it would make sense to replace that
"4" with a macro? Something like GMAC_RXQCTRL_PSRXQ_MAXCTRL2QUEUE?
> GMAC_RXQCTRL_PSRQX_MASK(queue);
> - writel(value, ioaddr + base_register);
> +
> + writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
> + writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
I suppose that the order of these two writes are somehow important, else these
could be factored out of the conditional block. Could you maybe add a short
comment that explains why the order of these writes matter?
Best Regards,
--
Romain Gantois, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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