netdev - Re: [PATCH net-next v3 3/6] net: hisilicon: add support for hisi

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Message-ID:
 <SEZPR06MB6959E5BDA57AF61BFAB19FC096512@SEZPR06MB6959.apcprd06.prod.outlook.com>
Date: Tue, 20 Feb 2024 05:19:12 +0800
From: Yang Xiwen <forbidden405@...look.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yisen Zhuang <yisen.zhuang@...wei.com>,
 Salil Mehta <salil.mehta@...wei.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Heiner Kallweit <hkallweit1@...il.com>,
 Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 3/6] net: hisilicon: add support for
 hisi_femac core on Hi3798MV200

On 2/20/2024 5:05 AM, Andrew Lunn wrote:
> On Tue, Feb 20, 2024 at 04:14:36AM +0800, Yang Xiwen wrote:
>> On 2/20/2024 4:03 AM, Andrew Lunn wrote:
>>>> Note it's unable to put the MDIO bus node outside of MAC controller
>>>> (i.e. at the same level in the parent bus node). Because we need to
>>>> control all clocks and resets in FEMAC driver due to the phy reset
>>>> procedure. So the clocks can't be assigned to MDIO bus device, which is
>>>> an essential resource for the MDIO bus to work.
>>> What PHY driver is being used? If there a specific PHY driver for this
>>> hardware? Does it implement soft reset?
>> I'm using generic PHY driver.
>>
>> It implements IEEE C22 standard. So there is a soft reset in BMCR register.
>>
>>> I'm wondering if you can skip hardware reset of the PHY and only do a
>>> software reset.
>> There must be someone to deassert the hardware reset control signal for the
>> PHY. We can't rely on the boot loader to do that. And here even we choose to
>> skip the hardware reset procedure, the sequence of deasserting the reset
>> signals is also very important. (i.e. first PHY, then MAC and MACIF).
>> Opposite to the normal sequence. (we normally first register MAC driver, and
>> then PHY).
> There are a few MACs which require the PHY to provide a clock to the
> MAC before they can use their DMA engine. The PHY provides typically a
> 25MHz clock, which is used to driver the DMA. So long as you don't
> touch the DMA, you can access other parts of the MAC before the PHY is
> generating the clock.
>
> So it might be possible to take the MAC and MACIF out of reset, then
> create the MDIO bus, probe the PHY, take it out of reset so its
> generating the clock, and then complete the rest of the MAC setup.

It's not MAC which behaves wrongly, it's the MDIO bus. If we don't 
follow the reset procedure properly. The MDIO bus fails to respond to 
any write/read commands. But i believe MAC controller and PHY are still 
working. I recalled that it can still transfer network packets, though 
it fails to read PHY registers from MDIO bus so only 10Mbps is available 
(And the phy id read out is always 0x0, normally it's 0x20669853).

Maybe during initialization, PHY sent some garbage to MDIO bus and 
killed it.

>
> 	Andrew
>

-- 
Regards,
Yang Xiwen