netdev - Re: [PATCH net-next v3 3/6] net: hisilicon: add support for hisi

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Message-ID:
 <SEZPR06MB695926ACA91530EB8642A30F96512@SEZPR06MB6959.apcprd06.prod.outlook.com>
Date: Tue, 20 Feb 2024 06:31:51 +0800
From: Yang Xiwen <forbidden405@...look.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yisen Zhuang <yisen.zhuang@...wei.com>,
 Salil Mehta <salil.mehta@...wei.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Heiner Kallweit <hkallweit1@...il.com>,
 Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 3/6] net: hisilicon: add support for
 hisi_femac core on Hi3798MV200

On 2/20/2024 6:05 AM, Andrew Lunn wrote:
>> It's not MAC which behaves wrongly, it's the MDIO bus. If we don't follow
>> the reset procedure properly. The MDIO bus fails to respond to any
>> write/read commands. But i believe MAC controller and PHY are still working.
>> I recalled that it can still transfer network packets, though it fails to
>> read PHY registers from MDIO bus so only 10Mbps is available (And the phy id
>> read out is always 0x0, normally it's 0x20669853).
>>
>> Maybe during initialization, PHY sent some garbage to MDIO bus and killed
>> it.
> MDIO bus masters are really simple things, not much more than a shift
> register. I find it hard to believe the MDIO bus master breaks because
> of reset order. If the MDIO pins went to SoC pins, it would be simple
> to prove, a bus-pirate or similar can capture the signals and sigrok
> can decode MDIO.
>
> To me, its more likely the PHY side of the MDIO bus is broken somehow.

The MDIO pins are not accessible from outside, only PHY pins are exported.

Maybe. I've tried many different approaches before i sent this patch. 
This is almost the only simple way i can implement to make it work. The 
downstream is also not telling us why it is needed to disable MAC 
controller before PHY reset. But it is mandatory. All i can do is to 
guess, unless HiSilicon people can join this conversion and tell us why. 
So the conclusion i got from trial and error is that MAC controller MUST 
be disabled during PHY reset, no matter what the reason is. I hope we 
can have the framework providing utilities for me to resolve this (e.g. 
provide a custom callback for PHY reset, in mdio_device_reset() function).

Also it's very strange that, if the PHY is reset in a wrong order, (i.e. 
Now we can not operate MDIO bus), we have to do the PHY reset procedure 
once again, simply resetting MAC does not work. So it might also be the 
PHY which is broken (partially).

>
>     Andrew

-- 
Regards,
Yang Xiwen