netdev - Re: [PATCH net-next v2 3/4] net: macb: Enable queue disable and WOL

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Message-ID: <8c0efb9a-d92c-4b9b-be75-498d460f67bd@lunn.ch>
Date: Fri, 23 Feb 2024 14:26:50 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Vineeth Karumanchi <vineeth.karumanchi@....com>
Cc: nicolas.ferre@...rochip.com, claudiu.beznea@...on.dev,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	linux@...linux.org.uk, vadim.fedorenko@...ux.dev,
	netdev@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, git@....com
Subject: Re: [PATCH net-next v2 3/4] net: macb: Enable queue disable and WOL

> It is not specific to AMD versions. All Cadence GEM IP versions have the
> capability, but specific vendors might enable or disable it as per their
> requirements.

Do you mean it is an option to synthesizer it or not? So although the
basic IP licensed from Cadence has it, a silicon vendor could remove
it?

> WOL was previously enabled via the device-tree attribute. Some users might
> not leverage it.

This is not typical. If the hardware supports it, we let the end user
decided if they want to use it or not.

So if all silicon should have it, enable it everywhere. If there is an
option to save some gates and leave it out of the silicon, then we do
need some per device knowledge, or a register which tells us what the
synthesis options where.

	Andrew