netdev - Re: [PATCH net-next v3 04/10] net: ti: icssg-prueth: Add SR1.0-specific configuration bits

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Message-ID: <5337e08b-a4dd-46d0-bc2e-a30b82aeeb15@kernel.org>
Date: Mon, 26 Feb 2024 19:23:54 +0200
From: Roger Quadros <rogerq@...nel.org>
To: Diogo Ivo <diogo.ivo@...mens.com>, danishanwar@...com,
 davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
 pabeni@...hat.com, andrew@...n.ch, linux-arm-kernel@...ts.infradead.org,
 netdev@...r.kernel.org
Cc: jan.kiszka@...mens.com
Subject: Re: [PATCH net-next v3 04/10] net: ti: icssg-prueth: Add
 SR1.0-specific configuration bits

Hi Diogo,

On 21/02/2024 17:24, Diogo Ivo wrote:
> Define the firmware configuration structure and commands needed to
> communicate with SR1.0 firmware, as well as SR1.0 buffer information
> where it differs from SR2.0.
> 
> Based on the work of Roger Quadros, Murali Karicheri and
> Grygorii Strashko in TI's 5.10 SDK [1].
> 
> [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/?h=ti-linux-5.10.y
> 
> Co-developed-by: Jan Kiszka <jan.kiszka@...mens.com>
> Signed-off-by: Jan Kiszka <jan.kiszka@...mens.com>
> Signed-off-by: Diogo Ivo <diogo.ivo@...mens.com>
> ---
> Changes in v2:
>  - Removed explicit references to SR2.0
> 
>  drivers/net/ethernet/ti/icssg/icssg_config.h | 56 ++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/drivers/net/ethernet/ti/icssg/icssg_config.h b/drivers/net/ethernet/ti/icssg/icssg_config.h
> index 43eb0922172a..cb465b3f5355 100644
> --- a/drivers/net/ethernet/ti/icssg/icssg_config.h
> +++ b/drivers/net/ethernet/ti/icssg/icssg_config.h
> @@ -35,6 +35,23 @@ struct icssg_flow_cfg {
>  	(2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \
>  	 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2))
>  
> +/* SR1.0 defines */
> +#define PRUETH_MAX_RX_FLOWS_SR1		4	/* excluding default flow */
> +#define PRUETH_RX_FLOW_DATA_SR1		3       /* highest priority flow */
> +#define PRUETH_MAX_RX_MGM_DESC		8
> +#define PRUETH_MAX_RX_MGM_FLOWS		2	/* excluding default flow */
> +#define PRUETH_RX_MGM_FLOW_RESPONSE	0
> +#define PRUETH_RX_MGM_FLOW_TIMESTAMP	1

Should we add suffix _SR1 to all SR1 specific macro names?

> +
> +#define PRUETH_NUM_BUF_POOLS_SR1		16
> +#define PRUETH_EMAC_BUF_POOL_START_SR1		8
> +#define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1	128
> +#define PRUETH_EMAC_BUF_SIZE_SR1		1536
> +#define PRUETH_EMAC_NUM_BUF_SR1			4
> +#define PRUETH_EMAC_BUF_POOL_SIZE_SR1	(PRUETH_EMAC_NUM_BUF_SR1 * \
> +					 PRUETH_EMAC_BUF_SIZE_SR1)
> +#define MSMC_RAM_SIZE_SR1	(SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */
> +
>  struct icssg_rxq_ctx {
>  	__le32 start[3];
>  	__le32 end;
> @@ -104,6 +121,45 @@ enum icssg_port_state_cmd {
>  #define ICSSG_NUM_NORMAL_PDS	64
>  #define ICSSG_NUM_SPECIAL_PDS	16
>  
> +struct icssg_sr1_config {
> +	__le32 status;		/* Firmware status */
> +	__le32 addr_lo;		/* MSMC Buffer pool base address low. */
> +	__le32 addr_hi;		/* MSMC Buffer pool base address high. Must be 0 */
> +	__le32 tx_buf_sz[16];	/* Array of buffer pool sizes */
> +	__le32 num_tx_threads;	/* Number of active egress threads, 1 to 4 */
> +	__le32 tx_rate_lim_en;	/* Bitmask: Egress rate limit en per thread */
> +	__le32 rx_flow_id;	/* RX flow id for first rx ring */
> +	__le32 rx_mgr_flow_id;	/* RX flow id for the first management ring */
> +	__le32 flags;		/* TBD */
> +	__le32 n_burst;		/* for debug */
> +	__le32 rtu_status;	/* RTU status */
> +	__le32 info;		/* reserved */
> +	__le32 reserve;
> +	__le32 rand_seed;	/* Used for the random number generation at fw */
> +} __packed;
> +
> +/* SR1.0 shutdown command to stop processing at firmware.
> + * Command format: 0x8101ss00, where
> + *	- ss: sequence number. Currently not used by driver.
> + */
> +#define ICSSG_SHUTDOWN_CMD		0x81010000
> +
> +/* SR1.0 pstate speed/duplex command to set speed and duplex settings
> + * in firmware.
> + * Command format: 0x8102ssPN, where
> + *	- ss: sequence number. Currently not used by driver.
> + *	- P: port number (for switch mode).
> + *	- N: Speed/Duplex state:
> + *		0x0 - 10Mbps/Half duplex;
> + *		0x8 - 10Mbps/Full duplex;
> + *		0x2 - 100Mbps/Half duplex;
> + *		0xa - 100Mbps/Full duplex;
> + *		0xc - 1Gbps/Full duplex;
> + *		NOTE: The above are the same value as bits [3..1](slice 0)
> + *		      or bits [7..5](slice 1) of RGMII CFG register.
> + */
> +#define ICSSG_PSTATE_SPEED_DUPLEX_CMD	0x81020000
> +

How about bunching all S1.0 related changes at one place in this file?

>  #define ICSSG_NORMAL_PD_SIZE	8
>  #define ICSSG_SPECIAL_PD_SIZE	20
>  

-- 
cheers,
-roger