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Message-ID:
<LV3P220MB12022BEFC410BCBCD52DD891A03D2@LV3P220MB1202.NAMP220.PROD.OUTLOOK.COM>
Date: Wed, 3 Apr 2024 16:05:16 -0400
From: Min Li <lnimi@...mail.com>
To: richardcochran@...il.com,
lee@...nel.org
Cc: linux-kernel@...r.kernel.org,
netdev@...r.kernel.org,
Min Li <min.li.xe@...esas.com>
Subject: [PATCH net 1/1] ptp: 82p33: move register definitions out of ptp folder
From: Min Li <min.li.xe@...esas.com>
Relocate register definitions so that other multi-functional
devices can access.
Signed-off-by: Min Li <min.li.xe@...esas.com>
---
drivers/ptp/ptp_idt82p33.h | 27 -----------------------
include/linux/mfd/idt82p33_reg.h | 38 +++++++++++++++++++++++++++++---
2 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h
index 6a63c14b6966..b4f3ee40389f 100644
--- a/drivers/ptp/ptp_idt82p33.h
+++ b/drivers/ptp/ptp_idt82p33.h
@@ -23,25 +23,6 @@
#define DDCO_THRESHOLD_NS (5)
#define IDT82P33_MAX_WRITE_COUNT (512)
-#define PLLMASK_ADDR_HI 0xFF
-#define PLLMASK_ADDR_LO 0xA5
-
-#define PLL0_OUTMASK_ADDR_HI 0xFF
-#define PLL0_OUTMASK_ADDR_LO 0xB0
-
-#define PLL1_OUTMASK_ADDR_HI 0xFF
-#define PLL1_OUTMASK_ADDR_LO 0xB2
-
-#define PLL2_OUTMASK_ADDR_HI 0xFF
-#define PLL2_OUTMASK_ADDR_LO 0xB4
-
-#define PLL3_OUTMASK_ADDR_HI 0xFF
-#define PLL3_OUTMASK_ADDR_LO 0xB6
-
-#define DEFAULT_PLL_MASK (0x01)
-#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
-#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
-
/**
* @brief Maximum absolute value for write phase offset in nanoseconds
*/
@@ -103,12 +84,4 @@ struct idt82p33 {
s64 tod_write_overhead_ns;
};
-/* firmware interface */
-struct idt82p33_fwrc {
- u8 hiaddr;
- u8 loaddr;
- u8 value;
- u8 reserved;
-} __packed;
-
#endif /* PTP_IDT82P33_H */
diff --git a/include/linux/mfd/idt82p33_reg.h b/include/linux/mfd/idt82p33_reg.h
index 1db532feeb91..15828e205fa8 100644
--- a/include/linux/mfd/idt82p33_reg.h
+++ b/include/linux/mfd/idt82p33_reg.h
@@ -22,6 +22,12 @@
#define DPLL1_OPERATING_MODE_CNFG 0x120
#define DPLL2_OPERATING_MODE_CNFG 0x1A0
+#define DPLL1_HOLDOVER_MODE_CNFG_LSB 0x12A
+#define DPLL1_HOLDOVER_MODE_CNFG_MSB 0x12B
+
+#define DPLL2_HOLDOVER_MODE_CNFG_LSB 0x1A9
+#define DPLL2_HOLDOVER_MODE_CNFG_MSB 0x1AA
+
#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
@@ -43,7 +49,6 @@
#define REG_SOFT_RESET 0X381
#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
-#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
/* Register bit definitions */
#define SYNC_TOD BIT(1)
@@ -101,7 +106,7 @@ enum hw_tod_trig_sel {
WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
};
-/** @brief Enumerated type listing DPLL operational modes */
+/* Enumerated type listing DPLL operational modes */
enum dpll_state {
DPLL_STATE_FREERUN = 1,
DPLL_STATE_HOLDOVER = 2,
@@ -109,7 +114,34 @@ enum dpll_state {
DPLL_STATE_PRELOCKED2 = 5,
DPLL_STATE_PRELOCKED = 6,
DPLL_STATE_LOSTPHASE = 7,
- DPLL_STATE_MAX
+ DPLL_STATE_MAX = DPLL_STATE_LOSTPHASE,
};
+/* firmware interface */
+struct idt82p33_fwrc {
+ u8 hiaddr;
+ u8 loaddr;
+ u8 value;
+ u8 reserved;
+} __packed;
+
+#define PLLMASK_ADDR_HI 0xFF
+#define PLLMASK_ADDR_LO 0xA5
+
+#define PLL0_OUTMASK_ADDR_HI 0xFF
+#define PLL0_OUTMASK_ADDR_LO 0xB0
+
+#define PLL1_OUTMASK_ADDR_HI 0xFF
+#define PLL1_OUTMASK_ADDR_LO 0xB2
+
+#define PLL2_OUTMASK_ADDR_HI 0xFF
+#define PLL2_OUTMASK_ADDR_LO 0xB4
+
+#define PLL3_OUTMASK_ADDR_HI 0xFF
+#define PLL3_OUTMASK_ADDR_LO 0xB6
+
+#define DEFAULT_PLL_MASK (0x01)
+#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
+#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
+
#endif
--
2.39.2
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