netdev - Re: [PATCH 1/3] net: dsa: microchip: lan9372: fix TX PHY access

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Date: Thu, 4 Apr 2024 03:41:21 +0000
From: <Arun.Ramadoss@...rochip.com>
To: <l.stach@...gutronix.de>, <olteanv@...il.com>,
	<Woojung.Huh@...rochip.com>, <UNGLinuxDriver@...rochip.com>,
	<andrew@...n.ch>, <f.fainelli@...il.com>
CC: <kernel@...gutronix.de>, <patchwork-lst@...gutronix.de>,
	<netdev@...r.kernel.org>
Subject: Re: [PATCH 1/3] net: dsa: microchip: lan9372: fix TX PHY access

On Wed, 2024-04-03 at 20:02 +0200, Lucas Stach wrote:
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> 
> On the LAN9372 the 4th internal PHY is a TX PHY instead of a T1 PHY.
> TX PHYs have a different base register offset.
> 
> Signed-off-by: Lucas Stach <l.stach@...gutronix.de>

As it is targetted net, it should have fixes tag. 

> ---
>  drivers/net/dsa/microchip/lan937x_main.c | 3 +++
>  drivers/net/dsa/microchip/lan937x_reg.h  | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c
> b/drivers/net/dsa/microchip/lan937x_main.c
> index b479a628b1ae..6a20cbacc513 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -55,6 +55,9 @@ static int lan937x_vphy_ind_addr_wr(struct
> ksz_device *dev, int addr, int reg)
>         u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
>         u16 temp;
> 
> +       if (dev->info->chip_id == LAN9372_CHIP_ID && addr == 3)
> +               addr_base = REG_PORT_TX_PHY_CTRL_BASE;

LAN9371 is similar to LAN9372, it also have 4th internal phy as Tx Phy.
Can you please add LAN9371 as well here. 

> +
>         /* get register address based on the logical port */
>         temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
> 
> diff --git a/drivers/net/dsa/microchip/lan937x_reg.h
> b/drivers/net/dsa/microchip/lan937x_reg.h
> index 45b606b6429f..7ecada924023 100644
> --- a/drivers/net/dsa/microchip/lan937x_reg.h
> +++ b/drivers/net/dsa/microchip/lan937x_reg.h
> @@ -147,6 +147,7 @@
> 
>  /* 1 - Phy */
>  #define REG_PORT_T1_PHY_CTRL_BASE      0x0100
> +#define REG_PORT_TX_PHY_CTRL_BASE      0x0280
> 
>  /* 3 - xMII */
>  #define PORT_SGMII_SEL                 BIT(7)
> --
> 2.39.2
>