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Message-ID: <cb2519c4-0514-4237-94f8-6707263806a1@lunn.ch>
Date: Fri, 5 Apr 2024 23:51:42 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Alexander Duyck <alexander.duyck@...il.com>
Cc: netdev@...r.kernel.org, Alexander Duyck <alexanderduyck@...com>,
kuba@...nel.org, davem@...emloft.net, pabeni@...hat.com
Subject: Re: [net-next PATCH 11/15] eth: fbnic: Enable Ethernet link setup
> +#define FBNIC_CSR_START_PCS 0x10000 /* CSR section delimiter */
> +#define FBNIC_PCS_CONTROL1_0 0x10000 /* 0x40000 */
> +#define FBNIC_PCS_CONTROL1_RESET CSR_BIT(15)
> +#define FBNIC_PCS_CONTROL1_LOOPBACK CSR_BIT(14)
> +#define FBNIC_PCS_CONTROL1_SPEED_SELECT_ALWAYS CSR_BIT(13)
> +#define FBNIC_PCS_CONTROL1_SPEED_ALWAYS CSR_BIT(6)
This appears to be PCS control register 1, define in 45.2.3.1. Since
this is a standard register, please add it to mdio.h.
> +#define FBNIC_PCS_VENDOR_VL_INTVL_0 0x10202 /* 0x40808 */
Could you explain how these registers map to 802.3 clause 45? Would
that be 3.1002? That would however put it in the reserved range 3.812
through 3.1799. The vendor range is 3.32768 through 3.65535.
> +#define FBNIC_PCS_VL0_0_CHAN_0 0x10208 /* 0x40820 */
> +#define FBNIC_PCS_VL0_1_CHAN_0 0x10209 /* 0x40824 */
> +#define FBNIC_PCS_VL1_0_CHAN_0 0x1020a /* 0x40828 */
> +#define FBNIC_PCS_VL1_1_CHAN_0 0x1020b /* 0x4082c */
> +#define FBNIC_PCS_VL2_0_CHAN_0 0x1020c /* 0x40830 */
> +#define FBNIC_PCS_VL2_1_CHAN_0 0x1020d /* 0x40834 */
> +#define FBNIC_PCS_VL3_0_CHAN_0 0x1020e /* 0x40838 */
> +#define FBNIC_PCS_VL3_1_CHAN_0 0x1020f /* 0x4083c */
> +#define FBNIC_PCS_MODE_VL_CHAN_0 0x10210 /* 0x40840 */
> +#define FBNIC_PCS_MODE_HI_BER25 CSR_BIT(2)
> +#define FBNIC_PCS_MODE_DISABLE_MLD CSR_BIT(1)
> +#define FBNIC_PCS_MODE_ENA_CLAUSE49 CSR_BIT(0)
> +#define FBNIC_PCS_CONTROL1_1 0x10400 /* 0x41000 */
> +#define FBNIC_PCS_VENDOR_VL_INTVL_1 0x10602 /* 0x41808 */
> +#define FBNIC_PCS_VL0_0_CHAN_1 0x10608 /* 0x41820 */
> +#define FBNIC_PCS_VL0_1_CHAN_1 0x10609 /* 0x41824 */
> +#define FBNIC_PCS_VL1_0_CHAN_1 0x1060a /* 0x41828 */
> +#define FBNIC_PCS_VL1_1_CHAN_1 0x1060b /* 0x4182c */
> +#define FBNIC_PCS_VL2_0_CHAN_1 0x1060c /* 0x41830 */
> +#define FBNIC_PCS_VL2_1_CHAN_1 0x1060d /* 0x41834 */
> +#define FBNIC_PCS_VL3_0_CHAN_1 0x1060e /* 0x41838 */
> +#define FBNIC_PCS_VL3_1_CHAN_1 0x1060f /* 0x4183c */
> +#define FBNIC_PCS_MODE_VL_CHAN_1 0x10610 /* 0x41840 */
> +#define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */
> +
> +#define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */
> +#define FBNIC_RSFEC_CONTROL(n)\
> + (0x10800 + 8 * (n)) /* 0x42000 + 32*n */
> +#define FBNIC_RSFEC_CONTROL_AM16_COPY_DIS CSR_BIT(3)
> +#define FBNIC_RSFEC_CONTROL_KP_ENABLE CSR_BIT(8)
> +#define FBNIC_RSFEC_CONTROL_TC_PAD_ALTER CSR_BIT(10)
> +#define FBNIC_RSFEC_MAX_LANES 4
> +#define FBNIC_RSFEC_CCW_LO(n) \
> + (0x10802 + 8 * (n)) /* 0x42008 + 32*n */
> +#define FBNIC_RSFEC_CCW_HI(n) \
> + (0x10803 + 8 * (n)) /* 0x4200c + 32*n */
Is this Corrected Code Words Lower/Upper? 1.202 and 1.203?
> +#define FBNIC_RSFEC_NCCW_LO(n) \
> + (0x10804 + 8 * (n)) /* 0x42010 + 32*n */
> +#define FBNIC_RSFEC_NCCW_HI(n) \
> + (0x10805 + 8 * (n)) /* 0x42014 + 32*n */
Which suggests this is Uncorrected code Words? 1.204, 1.205? I guess
the N is for Not?
> +#define FBNIC_RSFEC_SYMBLERR_LO(n) \
> + (0x10880 + 8 * (n)) /* 0x42200 + 32*n */
> +#define FBNIC_RSFEC_SYMBLERR_HI(n) \
> + (0x10881 + 8 * (n)) /* 0x42204 + 32*n */
And these are symbol count errors, 1.210 and 1.211?
If there are other registers which follow 802.3 it would be good to
add them to mdio.h, so others can share them.
Andrew
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