netdev - Re: [PATCH net-next v1 4/4] net: phy: add Applied Micro QT2025 PHY driver

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Message-ID: <0aa87df5-a2b8-45b8-a483-37eee86739bc@lunn.ch>
Date: Tue, 16 Apr 2024 14:08:32 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Trevor Gross <tmgross@...ch.edu>
Cc: FUJITA Tomonori <fujita.tomonori@...il.com>, netdev@...r.kernel.org,
	rust-for-linux@...r.kernel.org
Subject: Re: [PATCH net-next v1 4/4] net: phy: add Applied Micro QT2025 PHY
 driver

> > +        let mut a = MDIO_MMD_PCS;
> > +        for (i, val) in fw.data().iter().enumerate() {
> > +            if i == 0x4000 {
> > +                a = MDIO_MMD_PHYXS;
> > +                j = 0x8000;
> > +            }
> 
> Looks like firmware is split between PCS and PHYXS at 0x4000, but like
> Greg said you should probably explain where this comes from.
> 
> > +            dev.c45_write(a, j, (*val).into())?;
> 
> I think this is writing one byte at a time, to answer Andrew's
> question. Can you write a `u16::from_le_bytes(...)` to alternating
> addresses instead? This would be pretty easy by doing
> `fw.data().chunks(2)`.

That probably does not work, given my understanding of what is going
on. A C45 register is a u16.

The data sheet says:

  The 24kB of program memory space is accessible by
  MDIO. The first 16kB of memory is located in the
  address range 3.8000h - 3.BFFFh. The next 8kB of
  memory is located at 4.8000h - 4.9FFFh.

0x3bfff-0x3800 = 0x0x3fff = 16K.

So there are 16K u16 registers mapped onto 16K bytes of SRAM. So each
register holds one byte. Trying to write two bytes every other
register is not something which the datasheet talks about. So i doubt
it will work. Which is shame, because it would double the download
speed.

	Andrew