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Message-Id: <20240417-mcp251xfd-gpio-feature-v1-2-bc0c61fd0c80@ew.tq-group.com>
Date: Wed, 17 Apr 2024 15:43:55 +0200
From: Gregor Herburger <gregor.herburger@...tq-group.com>
To: Marc Kleine-Budde <mkl@...gutronix.de>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Thomas Kopp <thomas.kopp@...rochip.com>,
Vincent Mailhol <mailhol.vincent@...adoo.fr>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-can@...r.kernel.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux@...tq-group.com, gregor.herburger@...tq-group.com,
alexander.stein@...tq-group.com
Subject: [PATCH 2/4] can: mcp251xfd: mcp251xfd_regmap_crc_write():
workaround for errata 5
According to Errata DS80000789E 5 writing IOCON register using one SPI
write command clears LAT0/LAT1.
Errata Fix/Work Around suggests to write registers with single byte write
instructions. However, it seems that every write to the second byte
causes the overrite of LAT0/LAT1.
Never write byte 2 of IOCON register to avoid clearing of LAT0/LAT1.
Signed-off-by: Gregor Herburger <gregor.herburger@...tq-group.com>
---
drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 35 +++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
index 92b7bc7f14b9..ab4e372baffb 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
@@ -229,14 +229,47 @@ mcp251xfd_regmap_crc_gather_write(void *context,
return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
}
+static int
+mcp251xfd_regmap_crc_write_iocon(void *context, const void *data, size_t count)
+{
+ const size_t data_offset = sizeof(__be16) +
+ mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
+ u16 reg = *(u16 *)data;
+
+ /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0/LAT1
+ *
+ * According to Errata DS80000789E 5 writing IOCON register using one
+ * SPI write command clears LAT0/LAT1.
+ *
+ * Errata Fix/Work Around suggests to write registers with single byte
+ * write instructions. However, it seems that the byte at 0xe06(IOCON[23:16])
+ * is for read-only access and writing to it causes the cleraing of LAT0/LAT1.
+ */
+
+ /* Write IOCON[15:0] */
+ mcp251xfd_regmap_crc_gather_write(context, ®, 1,
+ data + data_offset, 2);
+ reg += 3;
+ /* Write IOCON[31:24] */
+ mcp251xfd_regmap_crc_gather_write(context, ®, 1,
+ data + data_offset + 3, 1);
+
+ return 0;
+}
+
static int
mcp251xfd_regmap_crc_write(void *context,
const void *data, size_t count)
{
const size_t data_offset = sizeof(__be16) +
mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
+ u16 reg = *(u16 *)data;
- return mcp251xfd_regmap_crc_gather_write(context,
+ if (reg == MCP251XFD_REG_IOCON)
+ return mcp251xfd_regmap_crc_write_iocon(context,
+ data, count);
+ else
+ return mcp251xfd_regmap_crc_gather_write(context,
data, data_offset,
data + data_offset,
count - data_offset);
--
2.34.1
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