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Message-ID: <zbs5vkzyuoyte5mr2pprf7xxahhuxlinvxe24h4oc6jeshwii5@ivqr45z27ef4>
Date: Fri, 3 May 2024 01:02:24 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Yanteng Si <siyanteng@...ngson.cn>
Cc: andrew@...n.ch, hkallweit1@...il.com, peppe.cavallaro@...com,
alexandre.torgue@...s.st.com, joabreu@...opsys.com, Jose.Abreu@...opsys.com,
chenhuacai@...nel.org, linux@...linux.org.uk, guyinggang@...ngson.cn,
netdev@...r.kernel.org, chris.chenfeiyang@...il.com, siyanteng01@...il.com
Subject: Re: [PATCH net-next v12 02/15] net: stmmac: Add multi-channel support
On Thu, Apr 25, 2024 at 09:01:55PM +0800, Yanteng Si wrote:
> DW GMAC v3.x multi-channels feature is implemented as multiple
> sets of the same CSRs. Here is only preliminary support, it will
> be useful for the driver further evolution and for the users
> having multi-channel DWGMAC v3.x devices.
Why do you call it "preliminary"? AFAICS it's a fully functional
support with no restrictions. Am I wrong?
I would reformulate the commit message as:
"DW GMAC v3.73 can be equipped with the Audio Video (AV) feature which
enables transmission of time-sensitive traffic over bridged local area
networks (DWC Ethernet QoS Product). In that case there can be up to two
additional DMA-channels available with no Tx COE support (unless there is
vendor-specific IP-core alterations). Each channel is implemented as a
separate Control and Status register (CSR) for managing the transmit and
receive functions, descriptor handling, and interrupt handling.
Add the multi-channels DW GMAC controllers support just by making sure the
already implemented DMA-configs are performed on the per-channel basis.
Note the only currently known instance of the multi-channel DW GMAC
IP-core is the LS2K2000 GNET controller, which has been released with the
vendor-specific feature extension of having eight DMA-channels. The device
support will be added in one of the following up commits."
>
> Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
> Signed-off-by: Yinggang Gu <guyinggang@...ngson.cn>
> Signed-off-by: Yanteng Si <siyanteng@...ngson.cn>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 +-
> .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 32 ++++++++++---------
> .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 20 ++++++++++--
> .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 30 ++++++++---------
> drivers/net/ethernet/stmicro/stmmac/hwif.h | 2 +-
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++--
> 6 files changed, 55 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> index d87079016952..cc93f73a380e 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -395,7 +395,7 @@ static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,
> writel(v, ioaddr + EMAC_TX_CTL1);
> }
>
> -static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
> +static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan)
> {
> u32 v;
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> index bb82ee9b855f..f161ec9ac490 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
> @@ -70,15 +70,17 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
> writel(value, ioaddr + DMA_AXI_BUS_MODE);
> }
>
> -static void dwmac1000_dma_init(void __iomem *ioaddr,
> - struct stmmac_dma_cfg *dma_cfg)
> +static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
> + void __iomem *ioaddr,
> + struct stmmac_dma_cfg *dma_cfg, u32 chan)
> {
> - u32 value = readl(ioaddr + DMA_BUS_MODE);
> int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
> int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
> + u32 value;
>
> - /*
> - * Set the DMA PBL (Programmable Burst Length) mode.
> + value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
> +
> + /* Set the DMA PBL (Programmable Burst Length) mode.
> *
> * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
> * post 3.5 mode bit acts as 8*PBL.
> @@ -104,10 +106,10 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
> if (dma_cfg->aal)
> value |= DMA_BUS_MODE_AAL;
>
> - writel(value, ioaddr + DMA_BUS_MODE);
> + writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
>
> /* Mask interrupts by writing to CSR7 */
> - writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
> + writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
> }
>
> static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
> @@ -116,7 +118,7 @@ static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
> dma_addr_t dma_rx_phy, u32 chan)
> {
> /* RX descriptor base address list must be written into DMA CSR3 */
> - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
> + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
> }
>
> static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> @@ -125,7 +127,7 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
> dma_addr_t dma_tx_phy, u32 chan)
> {
> /* TX descriptor base address list must be written into DMA CSR4 */
> - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
> + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
> }
>
> static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
> @@ -153,7 +155,7 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable RX store and forward mode\n");
> @@ -175,14 +177,14 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
> /* Configure flow control based on rx fifo size */
> csr6 = dwmac1000_configure_fc(csr6, fifosz);
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
> static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> void __iomem *ioaddr, int mode,
> u32 channel, int fifosz, u8 qmode)
> {
> - u32 csr6 = readl(ioaddr + DMA_CONTROL);
> + u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
>
> if (mode == SF_DMA_MODE) {
> pr_debug("GMAC: enable TX store and forward mode\n");
> @@ -209,7 +211,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
> csr6 |= DMA_CONTROL_TTC_256;
> }
>
> - writel(csr6, ioaddr + DMA_CONTROL);
> + writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
> }
>
Just figured out that besides of the channel-related changes you also need
to have the stmmac_dma_operation_mode() method fixed. So one wouldn't
redistribute the detected Tx/Rx FIFO between the channels. Each DW GMAC
channel has separate FIFO of the same size. The databook explicitly says
about that:
"The Tx FIFO size of all selected Transmit channels is always same.
Similarly, the Rx FIFO size of all selected Receive channels is same.
These channels cannot be of different sizes."
-Serge(y)
> [...]
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