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Message-ID: <62b19955-23b8-4cd1-b09c-68546f612b44@lunn.ch>
Date: Mon, 20 May 2024 15:33:53 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Sky Huang <SkyLake.Huang@...iatek.com>
Cc: Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Daniel Golle <daniel@...rotopia.org>,
Qingfang Deng <dqfext@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Steven Liu <Steven.Liu@...iatek.com>
Subject: Re: [PATCH net-next v3 5/5] net: phy: add driver for built-in 2.5G
ethernet PHY on MT7988
> +static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
> +{
> + struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
> + struct device *dev = &phydev->mdio.dev;
> + const struct firmware *fw;
> + struct pinctrl *pinctrl;
> + int ret, i;
> + u16 reg;
> +
> + if (!priv->fw_loaded) {
> + if (!priv->md32_en_cfg_base || !priv->pmb_addr) {
> + dev_err(dev, "MD32_EN_CFG base & PMB addresses aren't valid\n");
> + return -EINVAL;
> + }
> +
https://www.kernel.org/doc/html/latest/process/coding-style.html
6) Functions
Functions should be short and sweet, and do just one thing. They
should fit on one or two screenfuls of text (the ISO/ANSI screen
size is 80x24, as we all know), and do one thing and do that well.
This is a big function, which does multiple things. Maybe pull the
downloading of firmware into a helper.
> + ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
> + if (ret) {
> + dev_err(dev, "failed to load firmware: %s, ret: %d\n",
> + MT7988_2P5GE_PMB, ret);
> + return ret;
> + }
> +
> + if (fw->size != MT7988_2P5GE_PMB_SIZE) {
> + dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
> + fw->size, MT7988_2P5GE_PMB_SIZE);
> + return -EINVAL;
> + }
> +
> + reg = readw(priv->md32_en_cfg_base);
> + if (reg & MD32_EN) {
> + phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> + usleep_range(10000, 11000);
> + }
> + phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
> +
> + /* Write magic number to safely stall MCU */
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
> + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
> +
> + for (i = 0; i < MT7988_2P5GE_PMB_SIZE - 1; i += 4)
> + writel(*((uint32_t *)(fw->data + i)), priv->pmb_addr + i);
> + release_firmware(fw);
> +
> + writew(reg & ~MD32_EN, priv->md32_en_cfg_base);
> + writew(reg | MD32_EN, priv->md32_en_cfg_base);
> + phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
> + /* We need a delay here to stabilize initialization of MCU */
> + usleep_range(7000, 8000);
> + dev_info(dev, "Firmware loading/trigger ok.\n");
> +
> + priv->fw_loaded = true;
So there is no way to know if this has already happened? Maybe the
bootloader downloaded the firmware so it could TFTP boot? Linux will
download the firmware again, which is a waste of time.
> + iounmap(priv->md32_en_cfg_base);
> + iounmap(priv->pmb_addr);
> + }
> +
> + /* Setup LED */
> + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
> + MTK_PHY_LED_ON_POLARITY | MTK_PHY_LED_ON_LINK10 |
> + MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK1000 |
> + MTK_PHY_LED_ON_LINK2500);
> + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
> + MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX);
> +
> + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
Calls to devm_pinctrl_get_select() is pretty unusual in drivers:
https://elixir.bootlin.com/linux/latest/C/ident/devm_pinctrl_get_select
Why is this needed? Generally, the DT file should describe the needed
pinmux setting, without needed anything additionally.
> +static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = genphy_c45_pma_read_abilities(phydev);
> + if (ret)
> + return ret;
> +
> + /* We don't support HDX at MAC layer on mt7988. So mask phy's HDX capabilities here. */
So you make it clear, the MAC does not support half duplex. The MAC
should then remove it, not the PHY.
> + linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported);
> +
> + return 0;
> +}
> +
> +static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy actually
> + * hasn't finished AN. So use CL22's link update function instead.
> + */
> + ret = genphy_update_link(phydev);
> + if (ret)
> + return ret;
> +
> + phydev->speed = SPEED_UNKNOWN;
> + phydev->duplex = DUPLEX_UNKNOWN;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + /* We'll read link speed through vendor specific registers down below. So remove
> + * phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma (AN off).
> + */
> + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
> + ret = genphy_c45_read_lpa(phydev);
> + if (ret < 0)
> + return ret;
> +
> + /* Clause 45 doesn't define 1000BaseT support. Read the link partner's 1G
> + * advertisement via Clause 22
> + */
> + ret = phy_read(phydev, MII_STAT1000);
> + if (ret < 0)
> + return ret;
> + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
> + } else if (phydev->autoneg == AUTONEG_DISABLE) {
> + return -EOPNOTSUPP;
> + }
It is a bit late doing this now. The user requested this a long time
ago, and it will be hard to understand why it now returns EOPNOTSUPP.
You should check for AUTONEG_DISABLE in config_aneg() and return the
error there.
Andrew
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