netdev - Re: [PATCH net-next v1 4/4] net: phy: add Applied Micro QT2025 PHY driver

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Date: Fri, 24 May 2024 10:50:50 +0900 (JST)
From: FUJITA Tomonori <fujita.tomonori@...il.com>
To: andrew@...n.ch
Cc: tmgross@...ch.edu, fujita.tomonori@...il.com, netdev@...r.kernel.org,
 rust-for-linux@...r.kernel.org
Subject: Re: [PATCH net-next v1 4/4] net: phy: add Applied Micro QT2025 PHY
 driver

Hi,
Sorry for the long delay,

On Tue, 16 Apr 2024 14:08:32 +0200
Andrew Lunn <andrew@...n.ch> wrote:

>> > +        let mut a = MDIO_MMD_PCS;
>> > +        for (i, val) in fw.data().iter().enumerate() {
>> > +            if i == 0x4000 {
>> > +                a = MDIO_MMD_PHYXS;
>> > +                j = 0x8000;
>> > +            }
>> 
>> Looks like firmware is split between PCS and PHYXS at 0x4000, but like
>> Greg said you should probably explain where this comes from.
>> 
>> > +            dev.c45_write(a, j, (*val).into())?;
>> 
>> I think this is writing one byte at a time, to answer Andrew's
>> question. Can you write a `u16::from_le_bytes(...)` to alternating
>> addresses instead? This would be pretty easy by doing
>> `fw.data().chunks(2)`.
> 
> That probably does not work, given my understanding of what is going
> on. A C45 register is a u16.

Confirmed that it doesn't work.

After some experiments, I found that the PHY on my environment works
without the firmware loaded. So I'll remove the firmware code in v2.

I assume that there are PHYs that need the firmware because the
original driver loads the firmware. Thus I'll add the firmware support
in the future after the abstractions for the firmware API are merged,
which the Nova GPU team has been working on [1].

[1] https://lore.kernel.org/all/20240521212333.GA731457-robh@kernel.org/T/