Message-Id: <20240528-next-2024-05-28-ptp-refactors-v1-0-c082739bb6f6@intel.com>
Date: Tue, 28 May 2024 16:03:50 -0700
From: Jacob Keller <jacob.e.keller@...el.com>
To: David Miller <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, 
 netdev <netdev@...r.kernel.org>
Cc: Jacob Keller <jacob.e.keller@...el.com>, Jiri Pirko <jiri@...nulli.us>, 
 Karol Kolacinski <karol.kolacinski@...el.com>, 
 Przemek Kitszel <przemyslaw.kitszel@...el.com>, 
 Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>, 
 Pucha Himasekhar Reddy <himasekharx.reddy.pucha@...el.com>, 
 Sergey Temerkhanov <sergey.temerkhanov@...el.com>, 
 Michal Michalik <michal.michalik@...el.com>, 
 Grzegorz Nitka <grzegorz.nitka@...el.com>, 
 Prathisna Padmasanan <prathisna.padmasanan@...el.com>, 
 Pawel Kaminski <pawel.kaminski@...el.com>, 
 Mateusz Polchlopek <mateusz.polchlopek@...el.com>
Subject: [PATCH next 00/11] ice: Introduce ETH56G PHY model for E825C
 products

E825C products have a different PHY model than E822, E823 and E810 products.
This PHY is ETH56G and its support is necessary to have functional PTP stack
for E825C products.

This series refactors the ice driver to add support for the new PHY model.

Karol introduces the ice_ptp_hw structure. This is used to replace some
hard-coded values relating to the PHY quad and port numbers, as well as to
hold the phy_model type.

Jacob refactors the driver code that converts between the ice_ptp_tmr_cmd
enumeration and hardware register values to better re-use logic and reduce
duplication when introducing another PHY type.

Sergey introduces functions to help enable and disable the Tx timestamp
interrupts. This makes the ice_ptp.c code more generic and encapsulates the
PHY specifics into ice_ptp_hw.c

Karol introduces helper functions to clear the valid bits for Tx and Rx
timestamps. This enables informing hardware to discard stale timestamps
after performing clock operations.

Sergey moves the Clock Generation Unit (CGU) logic out of the E822 specific
area of the ice_ptp_hw.c file as it will be re-used for other device PHY
models.

Jacob introduces a helper function for obtaining the base increment values,
moving this logic out of ice_ptp.c and into the ice_ptp_hw.c file to better
encapsulate hardware differences.

Sergey builds on these refactors to introduce the new ETH56G PHY model used
by the E825C products. This includes introducing the required helpers,
constants, and PHY model checks.

Karol simplifies the CGU logic by using anonymous structures, dropping an
unnecessary ".field" name for accessing the CGU data.

Michal Michalik updates the CGU logic to support the E825C hardware,
ensuring that the clock generation is configured properly.

Grzegorz Nitka adds support to read the NAC topology data from the device.
This is in preparation for supporting devices which combine two NACs
together, connecting all ports to the same clock source. This enables the
driver to determine if its operating on such a device, or if its operating
on the standard 1-NAC configuration.

Grzsecgorz Nitka adjusts the PTP initialization to prepare for the 2x50G
E825C devices, introducing special mapping for the PHY ports to prepare for
support of the 2-NAC devices.

With this, the ice driver is capable of handling PTP for the single-NAC
E825C devices. Complete support for the 2-NAC devices requirs some work on
how the ports connect to the clock owner. During review of this work, it
was pointed out that our existing use of auxiliary bus is disliked, and
Jiri requested that we change it. We are currently working on developing a
replacement solution for the auxiliary bus implementation and have dropped
the relevant changes out of this series. A future series will refactor the
port to clock connection, at which time we will finish the support for
2-NAC E825C devices.

Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
---
Grzegorz Nitka (2):
      ice: Add NAC Topology device capability parser
      ice: Adjust PTP init for 2x50G E825C devices

Jacob Keller (2):
      ice: Introduce helper to get tmr_cmd_reg values
      ice: Introduce ice_get_base_incval() helper

Karol Kolacinski (3):
      ice: Introduce ice_ptp_hw struct
      ice: Add PHY OFFSET_READY register clearing
      ice: Change CGU regs struct to anonymous

Michal Michalik (1):
      ice: Add support for E825-C TS PLL handling

Sergey Temerkhanov (3):
      ice: Implement Tx interrupt enablement functions
      ice: Move CGU block
      ice: Introduce ETH56G PHY model for E825C products

 drivers/net/ethernet/intel/ice/ice_adminq_cmd.h |    1 +
 drivers/net/ethernet/intel/ice/ice_cgu_regs.h   |   77 +-
 drivers/net/ethernet/intel/ice/ice_common.c     |   74 +-
 drivers/net/ethernet/intel/ice/ice_common.h     |    2 +
 drivers/net/ethernet/intel/ice/ice_hw_autogen.h |    4 +
 drivers/net/ethernet/intel/ice/ice_ptp.c        |  208 +-
 drivers/net/ethernet/intel/ice/ice_ptp.h        |    1 +
 drivers/net/ethernet/intel/ice/ice_ptp_consts.h |  402 +++
 drivers/net/ethernet/intel/ice/ice_ptp_hw.c     | 3256 +++++++++++++++++++----
 drivers/net/ethernet/intel/ice/ice_ptp_hw.h     |  295 +-
 drivers/net/ethernet/intel/ice/ice_sbq_cmd.h    |   10 +-
 drivers/net/ethernet/intel/ice/ice_type.h       |   58 +-
 12 files changed, 3754 insertions(+), 634 deletions(-)
---
base-commit: 4b3529edbb8ff069d762c6947e055e10c1748170
change-id: 20240528-next-2024-05-28-ptp-refactors-49c37676fb59

Best regards,
-- 
Jacob Keller <jacob.e.keller@...el.com>

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