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Message-ID: <6d60bbc6-5ed3-4bb1-ad72-18a2be140b81@denx.de>
Date: Fri, 7 Jun 2024 14:48:58 +0200
From: Marek Vasut <marex@...x.de>
To: Christophe Roullier <christophe.roullier@...s.st.com>,
"David S . Miller" <davem@...emloft.net>, Eric Dumazet
<edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Richard Cochran <richardcochran@...il.com>, Jose Abreu
<joabreu@...opsys.com>, Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 09/12] ARM: dts: stm32: add ethernet1 and ethernet2
support on stm32mp13
On 6/7/24 11:57 AM, Christophe Roullier wrote:
[...]
> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@...07000 {
> status = "disabled";
> };
>
> + ethernet1: ethernet@...0a000 {
> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
> + reg = <0x5800a000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <&exti 68 1>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + clock-names = "stmmaceth",
> + "mac-clk-tx",
> + "mac-clk-rx",
> + "ethstp",
> + "eth-ck";
> + clocks = <&rcc ETH1MAC>,
> + <&rcc ETH1TX>,
> + <&rcc ETH1RX>,
> + <&rcc ETH1STP>,
> + <&rcc ETH1CK_K>;
> + st,syscon = <&syscfg 0x4 0xff0000>;
> + snps,mixed-burst;
> + snps,pbl = <2>;
> + snps,axi-config = <&stmmac_axi_config_1>;
> + snps,tso;
> + access-controllers = <&etzpc 48>;
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