netdev - Re: [PATCH v5 09/12] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Mon, 10 Jun 2024 12:37:04 +0200
From: Marek Vasut <marex@...x.de>
To: Alexandre TORGUE <alexandre.torgue@...s.st.com>,
 Christophe Roullier <christophe.roullier@...s.st.com>,
 "David S . Miller" <davem@...emloft.net>, Eric Dumazet
 <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Maxime Coquelin <mcoquelin.stm32@...il.com>,
 Richard Cochran <richardcochran@...il.com>, Jose Abreu
 <joabreu@...opsys.com>, Liam Girdwood <lgirdwood@...il.com>,
 Mark Brown <broonie@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
 linux-stm32@...md-mailman.stormreply.com,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 09/12] ARM: dts: stm32: add ethernet1 and ethernet2
 support on stm32mp13

On 6/10/24 10:06 AM, Alexandre TORGUE wrote:
> Hi Marek

Hi,

> On 6/7/24 14:48, Marek Vasut wrote:
>> On 6/7/24 11:57 AM, Christophe Roullier wrote:
>>
>> [...]
>>
>>> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@...07000 {
>>>                   status = "disabled";
>>>               };
> no space here ?
>>> +            ethernet1: ethernet@...0a000 {
>>> +                compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
>>> +                reg = <0x5800a000 0x2000>;
>>> +                reg-names = "stmmaceth";
>>> +                interrupts-extended = <&intc GIC_SPI 62 
>>> IRQ_TYPE_LEVEL_HIGH>,
>>> +                              <&exti 68 1>;
>>> +                interrupt-names = "macirq", "eth_wake_irq";
>>> +                clock-names = "stmmaceth",
>>> +                          "mac-clk-tx",
>>> +                          "mac-clk-rx",
>>> +                          "ethstp",
>>> +                          "eth-ck";
>>> +                clocks = <&rcc ETH1MAC>,
>>> +                     <&rcc ETH1TX>,
>>> +                     <&rcc ETH1RX>,
>>> +                     <&rcc ETH1STP>,
>>> +                     <&rcc ETH1CK_K>;
>>> +                st,syscon = <&syscfg 0x4 0xff0000>;
>>> +                snps,mixed-burst;
>>> +                snps,pbl = <2>;
>>> +                snps,axi-config = <&stmmac_axi_config_1>;
>>> +                snps,tso;
>>> +                access-controllers = <&etzpc 48>;
>>
>> Keep the list sorted.
> 
> The list is currently not sorted. I agree that it is better to have a 
> common rule to easy the read but it should be applied to all the nodes 
> for the whole STM32 family. Maybe to address by another series. For the 
> time being we can keep it as it is.

Why is the st,... and snps,... swapped anyway ? That can be fixed right 
here.

Why is the access-controllers at the end ? That can be fixed in separate 
series, since that seems to have proliferated considerably.