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Message-ID: <ae8ac05a56f479286bc748fb930c5643a2fbde10.1718696209.git.lorenzo@kernel.org>
Date: Tue, 18 Jun 2024 09:49:02 +0200
From: Lorenzo Bianconi <lorenzo@...nel.org>
To: netdev@...r.kernel.org
Cc: nbd@....name,
lorenzo.bianconi83@...il.com,
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kuba@...nel.org,
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Subject: [PATCH v2 net-next 1/2] dt-bindings: net: airoha: Add EN7581 ethernet controller
Introduce device-tree binding documentation for Airoha EN7581 ethernet
mac controller.
Signed-off-by: Lorenzo Bianconi <lorenzo@...nel.org>
---
This patch is based on the following one not applied yet on clk tree:
dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
https://patchwork.kernel.org/project/linux-clk/patch/ac557b6f4029cb3428d4c0ed1582d0c602481fb6.1718282056.git.lorenzo@kernel.org/
---
.../bindings/net/airoha,en7581.yaml | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581.yaml
diff --git a/Documentation/devicetree/bindings/net/airoha,en7581.yaml b/Documentation/devicetree/bindings/net/airoha,en7581.yaml
new file mode 100644
index 000000000000..09e7b5eed3ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,en7581.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,en7581.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Frame Engine Ethernet controller
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@...nel.org>
+
+description:
+ The frame engine ethernet controller can be found on Airoha SoCs.
+ These SoCs have dual GMAC ports.
+
+properties:
+ compatible:
+ enum:
+ - airoha,en7581-eth
+
+ reg:
+ items:
+ - description: Frame engine base address
+ - description: QDMA0 base address
+ - description: QDMA1 base address
+
+ reg-names:
+ items:
+ - const: fe
+ - const: qdma0
+ - const: qdma1
+
+ interrupts:
+ maxItems: 10
+
+ resets:
+ maxItems: 7
+
+ reset-names:
+ items:
+ - const: fe
+ - const: pdma
+ - const: qdma
+ - const: xsi-mac
+ - const: hsi0-mac
+ - const: hsi1-mac
+ - const: hsi-mac
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/en7523-clk.h>
+ #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ eth0: ethernet@...50000 {
+ compatible = "airoha,en7581-eth";
+ reg = <0 0x1fb50000 0 0x2600>,
+ <0 0x1fb54000 0 0x2000>,
+ <0 0x1fb56000 0 0x2000>;
+ reg-names = "fe", "qdma0", "qdma1";
+
+ resets = <&scuclk EN7581_FE_RST>,
+ <&scuclk EN7581_FE_PDMA_RST>,
+ <&scuclk EN7581_FE_QDMA_RST>,
+ <&scuclk EN7581_XSI_MAC_RST>,
+ <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
+ <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
+ <&scuclk EN7581_HSI_MAC_RST>;
+ reset-names = "fe", "pdma", "qdma", "xsi-mac",
+ "hsi0-mac", "hsi1-mac", "hsi-mac";
+
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
--
2.45.1
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