netdev - Re: [net-next,PATCH 2/2] net: stmmac: dwmac-stm32: stm32: add management of stm32mp25 for stm32

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Date: Tue, 18 Jun 2024 11:09:36 +0200
From: Christophe ROULLIER <christophe.roullier@...s.st.com>
To: Marek Vasut <marex@...x.de>, "David S . Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
        Paolo
 Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre
 Torgue <alexandre.torgue@...s.st.com>,
        Richard Cochran
	<richardcochran@...il.com>,
        Jose Abreu <joabreu@...opsys.com>,
        Liam Girdwood
	<lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [net-next,PATCH 2/2] net: stmmac: dwmac-stm32: stm32: add
 management of stm32mp25 for stm32

Hi Marek,

On 6/17/24 17:57, Marek Vasut wrote:
> On 6/17/24 1:23 PM, Christophe ROULLIER wrote:
>
> Hi,
>
>>>> +static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data 
>>>> *plat_dat)
>>>> +{
>>>> +    struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
>>>> +    u32 reg = dwmac->mode_reg;
>>>> +    int val = 0;
>>>> +
>>>> +    switch (plat_dat->mac_interface) {
>>>> +    case PHY_INTERFACE_MODE_MII:
>>>> +        break;
>>>
>>> dwmac->enable_eth_ck does not apply to MII mode ? Why ?
>>
>> It is like MP1 and MP13, nothing to set in syscfg register for case 
>> MII mode wo crystal.
>
> Have a look at STM32MP15xx RM0436 Figure 83. Peripheral clock 
> distribution for Ethernet.
>
> If RCC (top-left corner of the figure) generates 25 MHz MII clock 
> (yellow line) on eth_clk_fb (top-right corner), can I set 
> ETH_REF_CLK_SEL to position '1' and ETH_SEL[2] to '0' and feed ETH 
> (right side) clk_rx_i input with 25 MHz clock that way ?
>
> I seems like this should be possible, at least theoretically. Can you 
> check with the hardware/silicon people ?
No it is not possible (it will work if speed (and frequency) is fixed  
25Mhz=100Mbps, but for speed 10Mbps (2,5MHz) it will not work. (you can 
see than diviser are only for RMII mode)
>
> As a result, the MII/RMII mode would behave in a very similar way, and 
> so would GMII/RGMII mode behave in a very similar way. Effectively you 
> would end up with this (notice the fallthrough statements):
>
> +    case PHY_INTERFACE_MODE_RMII:
> +        val = SYSCFG_ETHCR_ETH_SEL_RMII;
> +        fallthrough;
> +    case PHY_INTERFACE_MODE_MII:
> +        if (dwmac->enable_eth_ck)
> +            val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;
> +        break;
> +
> +    case PHY_INTERFACE_MODE_RGMII:
> +    case PHY_INTERFACE_MODE_RGMII_ID:
> +    case PHY_INTERFACE_MODE_RGMII_RXID:
> +    case PHY_INTERFACE_MODE_RGMII_TXID:
> +        val = SYSCFG_ETHCR_ETH_SEL_RGMII;
> +        fallthrough;
> +    case PHY_INTERFACE_MODE_GMII:
> +        if (dwmac->enable_eth_ck)
> +            val |= SYSCFG_ETHCR_ETH_CLK_SEL;
> +        break;
>
> [...]