netdev - Re: [net-next,PATCH 2/2] net: stmmac: dwmac-stm32: stm32: add management of stm32mp25 for stm32

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Message-ID: <aee3f6d2-6a44-4de6-9348-f83c4107188f@foss.st.com>
Date: Wed, 19 Jun 2024 09:41:38 +0200
From: Christophe ROULLIER <christophe.roullier@...s.st.com>
To: Marek Vasut <marex@...x.de>, "David S . Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
        Paolo
 Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre
 Torgue <alexandre.torgue@...s.st.com>,
        Richard Cochran
	<richardcochran@...il.com>,
        Jose Abreu <joabreu@...opsys.com>,
        Liam Girdwood
	<lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [net-next,PATCH 2/2] net: stmmac: dwmac-stm32: stm32: add
 management of stm32mp25 for stm32

Hi Marek,

On 6/18/24 17:00, Marek Vasut wrote:
> On 6/18/24 11:09 AM, Christophe ROULLIER wrote:
>
> Hi,
>
>>>>>> +static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data 
>>>>>> *plat_dat)
>>>>>> +{
>>>>>> +    struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
>>>>>> +    u32 reg = dwmac->mode_reg;
>>>>>> +    int val = 0;
>>>>>> +
>>>>>> +    switch (plat_dat->mac_interface) {
>>>>>> +    case PHY_INTERFACE_MODE_MII:
>>>>>> +        break;
>>>>>
>>>>> dwmac->enable_eth_ck does not apply to MII mode ? Why ?
>>>>
>>>> It is like MP1 and MP13, nothing to set in syscfg register for case 
>>>> MII mode wo crystal.
>>>
>>> Have a look at STM32MP15xx RM0436 Figure 83. Peripheral clock 
>>> distribution for Ethernet.
>>>
>>> If RCC (top-left corner of the figure) generates 25 MHz MII clock 
>>> (yellow line) on eth_clk_fb (top-right corner), can I set 
>>> ETH_REF_CLK_SEL to position '1' and ETH_SEL[2] to '0' and feed ETH 
>>> (right side) clk_rx_i input with 25 MHz clock that way ?
>>>
>>> I seems like this should be possible, at least theoretically. Can 
>>> you check with the hardware/silicon people ?
>> No it is not possible (it will work if speed (and frequency) is fixed 
>> 25Mhz=100Mbps, but for speed 10Mbps (2,5MHz) it will not work.
>
> Could the pll4_p_ck or pll3_q_ck generate either 25 MHz or 2.5 MHz as 
> needed in that case ? Then it would work, right ?

Yes you can set frequency you want for pll4 or pll3, if you set 25MHz 
and auto-negotiation of speed is 100Mbps it should work (pad ETH_CK of 
25MHz clock the PHY and eth_clk_fb set to 25MHz for clk_RX)

but if autoneg of speed is 10Mbps, then 2.5MHz is needed for clk_RX (you 
will provide 25Mhz). For RMII case, frequency from pll (eth_clk_fb) is 
automatically adjust in function of speed value, thanks to diviser /2, 
/20 with mac_speed_o.

>
>> (you can see than diviser are only for RMII mode)
>
> Do you refer to /2 and /20 dividers to the left of mac_speed_o[0] ?