netdev - Re: [PATCH v3 net-next 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

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Message-ID: <e203100f-7bdd-4512-8a05-9a33476db488@lunn.ch>
Date: Mon, 24 Jun 2024 17:57:21 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Lorenzo Bianconi <lorenzo@...nel.org>
Cc: netdev@...r.kernel.org, nbd@....name, lorenzo.bianconi83@...il.com,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, conor@...nel.org,
	linux-arm-kernel@...ts.infradead.org, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	devicetree@...r.kernel.org, catalin.marinas@....com,
	will@...nel.org, upstream@...oha.com,
	angelogioacchino.delregno@...labora.com,
	benjamin.larsson@...exis.eu, rkannoth@...vell.com,
	sgoutham@...vell.com
Subject: Re: [PATCH v3 net-next 2/2] net: airoha: Introduce ethernet support
 for EN7581 SoC

On Mon, Jun 24, 2024 at 01:55:10AM +0200, Lorenzo Bianconi wrote:
> > > +static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,
> > > +				    u32 port, u32 queue, u32 val)
> > > +{
> > > +	u32 orig_val, tmp, all_rsv, fq_limit;
> > > +	const u32 pse_port_oq_id[] = {
> > > +		PSE_PORT0_QUEUE,
> > > +		PSE_PORT1_QUEUE,
> > > +		PSE_PORT2_QUEUE,
> > > +		PSE_PORT3_QUEUE,
> > > +		PSE_PORT4_QUEUE,
> > > +		PSE_PORT5_QUEUE,
> > > +		PSE_PORT6_QUEUE,
> > > +		PSE_PORT7_QUEUE,
> > > +		PSE_PORT8_QUEUE,
> > > +		PSE_PORT9_QUEUE,
> > > +		PSE_PORT10_QUEUE
> > > +	};
> > 
> > > +static void airoha_fe_oq_rsv_init(struct airoha_eth *eth)
> > > +{
> > > +	int i;
> > > +
> > > +	/* hw misses PPE2 oq rsv */
> > > +	airoha_fe_set(eth, REG_FE_PSE_BUF_SET,
> > > +		      PSE_DEF_RSV_PAGE * PSE_PORT8_QUEUE);
> > > +
> > > +	for (i = 0; i < PSE_PORT0_QUEUE; i++)
> > > +		airoha_fe_set_pse_oq_rsv(eth, 0, i, 0x40);
> > > +	for (i = 0; i < PSE_PORT1_QUEUE; i++)
> > > +		airoha_fe_set_pse_oq_rsv(eth, 1, i, 0x40);
> > > +
> > > +	for (i = 6; i < PSE_PORT2_QUEUE; i++)
> > > +		airoha_fe_set_pse_oq_rsv(eth, 2, i, 0);
> > > +
> > > +	for (i = 0; i < PSE_PORT3_QUEUE; i++)
> > > +		airoha_fe_set_pse_oq_rsv(eth, 3, i, 0x40);
> > 
> > Code like this is making me wounder about the split between MAC
> > driver, DSA driver and DSA tag driver. Or if it should actually be a
> > pure switchdev driver?
> 
> airoha_eth driver implements just MAC features (FE and QDMA). Currently we only
> support the connection to the DSA switch (GDM1). EN7581 SoC relies on mt7530 driver
> for DSA (I have not posted the patch for mt7530 yet, I will do after airoha_eth
> ones).
 
> airoha_fe_oq_rsv_init() (we can improve naming here :) is supposed to configure
> hw pre-allocated memory for each queue available in Packet Switching Engine
> (PSE) ports. PSE ports are not switch ports, but SoC internal ports used to
> connect PSE to different modules. In particular, we are currently implementing
> just the two connections below:
> - CDM1 (port0) connects PSE to QDMA1
> - GDM1 (port1) connects PSE to MT7530 DSA switch
> 
> In the future we will post support for GDM2, GDM3 and GDM4 ports that are
> connecting PSE to exteranl PHY modules.

Is the PSE involved in WiFi? When you come to implement NAT offload,
etc, will that depend on the PSE?

Figure 9-1 of MT7981B_Wi-Fi6_Platform_Datasheet_Open_V1.0.pdf clearly
shows the PSE outside of the GMAC. I'm just wondering if the PSE
should be a driver, or library, of its own, which is then shared by
users, rather than being embedded in the MAC driver?

       Andrew