netdev - Re: [PATCH net-next v1 2/3] net: dsa: microchip: lan937x: force RGMII interface into PHY mode

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Message-ID: <Zn5hyR1AKV81nulo@pengutronix.de>
Date: Fri, 28 Jun 2024 09:10:01 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Vladimir Oltean <olteanv@...il.com>
Cc: "David S. Miller" <davem@...emloft.net>, Andrew Lunn <andrew@...n.ch>,
	Eric Dumazet <edumazet@...gle.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Woojung Huh <woojung.huh@...rochip.com>,
	Arun Ramadoss <arun.ramadoss@...rochip.com>,
	Lucas Stach <l.stach@...gutronix.de>, kernel@...gutronix.de,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
	UNGLinuxDriver@...rochip.com
Subject: Re: [PATCH net-next v1 2/3] net: dsa: microchip: lan937x: force
 RGMII interface into PHY mode

On Fri, Jun 28, 2024 at 01:25:43AM +0300, Vladimir Oltean wrote:
> On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote:
> > From: Lucas Stach <l.stach@...gutronix.de>
> > 
> > The register manual and datasheet documentation for the LAN937x series
> > disagree about the polarity of the MII mode strap. As a consequence
> > there are hardware designs that have the RGMII interface strapped into
> > MAC mode, which is a invalid configuration and will prevent the internal
> > clock from being fed into the port TX interface.
> > 
> > Force the MII mode to PHY for RGMII interfaces where this is the only
> > valid mode, to override the inproper strapping.
> > 
> > Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
> > Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> > ---
> 
> What's the difference between MAC mode and PHY mode with RGMII for this switch?

Let's take a step back. I'll describe first my initial findings, the symptoms,
and my new findings from today, so my argumentation and the patch itself should
be updated.

Initially, we identified that the RGMIIx_MODE[1,0] strap pins select between
RGMII, RMII, and MII. The MIIx_PHY_MODE pin configures PHY mode for MII or
clock direction in RMII but should have no effect in RGMII mode. However, if
MIIx_PHY_MODE = 1, RGMII exhibits the following symptoms:

- No signal on RGMII TXD[]
- No TX counters increase on the related MAC port.
- RX interface works, and data from the CPU through the switch is properly
  accounted for.

Due to the absence of TX counters even for broadcast traffic, we interpreted
this as a disabled MAC TX functionality or disabled TX clock for the MAC. This
issue was resolved by unsetting Bit 2 on register 0x301, which is undocumented
for RGMII.

Now, comparing LAN937x documentation with publicly available documentation for
other switches, for example KSZ9893R, may give some clue on the undocumented
part in the LAN937x datasheet:
RGMII Interface:
 1 = In-Band Status (IBS) enabled (requires IBS-capable PHY)
 0 = IBS disabled

The issue likely stems from active IBS mode, confirmed by an article
recommending IBS disablement via register 0x302.
https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed

The same effect seems to be achieved by toggling the undocumented 0x301 bit 2.
The ksz_set_xmii() function contains existing code to handle this:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	    data8 |= bitval[P_RGMII_SEL];
	    /* On KSZ9893, disable RGMII in-band status support */
	    if (dev->chip_id == KSZ9893_CHIP_ID ||
		dev->chip_id == KSZ8563_CHIP_ID ||
		dev->chip_id == KSZ9563_CHIP_ID)
		data8 &= ~P_MII_MAC_MODE;
	    break;
	default:

Regards,
Oleksij
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