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Message-ID: <Zn5wErirnIlkzaoj@lore-desk>
Date: Fri, 28 Jun 2024 10:10:58 +0200
From: Lorenzo Bianconi <lorenzo@...nel.org>
To: Rob Herring <robh@...nel.org>
Cc: netdev@...r.kernel.org, nbd@....name, lorenzo.bianconi83@...il.com,
davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
pabeni@...hat.com, conor@...nel.org,
linux-arm-kernel@...ts.infradead.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
devicetree@...r.kernel.org, catalin.marinas@....com,
will@...nel.org, upstream@...oha.com,
angelogioacchino.delregno@...labora.com,
benjamin.larsson@...exis.eu, rkannoth@...vell.com,
sgoutham@...vell.com, andrew@...n.ch
Subject: Re: [PATCH v3 net-next 1/2] dt-bindings: net: airoha: Add EN7581
ethernet controller
> On Sun, Jun 23, 2024 at 06:19:56PM +0200, Lorenzo Bianconi wrote:
> > Introduce device-tree binding documentation for Airoha EN7581 ethernet
> > mac controller.
> >
> > Signed-off-by: Lorenzo Bianconi <lorenzo@...nel.org>
> > ---
> > .../bindings/net/airoha,en7581-eth.yaml | 108 ++++++++++++++++++
> > 1 file changed, 108 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > new file mode 100644
> > index 000000000000..e25a462a75d4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Airoha EN7581 Frame Engine Ethernet controller
> > +
> > +allOf:
> > + - $ref: ethernet-controller.yaml#
> > +
> > +maintainers:
> > + - Lorenzo Bianconi <lorenzo@...nel.org>
> > +
> > +description:
> > + The frame engine ethernet controller can be found on Airoha SoCs.
> > + These SoCs have dual GMAC ports.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - airoha,en7581-eth
> > +
> > + reg:
> > + items:
> > + - description: Frame engine base address
> > + - description: QDMA0 base address
> > + - description: QDMA1 base address
> > +
> > + reg-names:
> > + items:
> > + - const: fe
> > + - const: qdma0
> > + - const: qdma1
> > +
> > + interrupts:
> > + maxItems: 10
>
> You need to define what each interrupt is. Just like 'reg'.
ack, I will fix it in v4.
>
> > +
> > + resets:
> > + maxItems: 8
> > +
> > + reset-names:
> > + items:
> > + - const: fe
> > + - const: pdma
> > + - const: qdma
> > + - const: xsi-mac
> > + - const: hsi0-mac
> > + - const: hsi1-mac
> > + - const: hsi-mac
> > + - const: xfp-mac
> > +
>
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 0
>
> What are these for? You have no child nodes to use them.
ack, in v4 I will add mac ethernet subnode.
Regards,
Lorenzo
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - resets
> > + - reset-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/clock/en7523-clk.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + eth0: ethernet@...50000 {
> > + compatible = "airoha,en7581-eth";
> > + reg = <0 0x1fb50000 0 0x2600>,
> > + <0 0x1fb54000 0 0x2000>,
> > + <0 0x1fb56000 0 0x2000>;
> > + reg-names = "fe", "qdma0", "qdma1";
> > +
> > + resets = <&scuclk 44>,
> > + <&scuclk 30>,
> > + <&scuclk 31>,
> > + <&scuclk 6>,
> > + <&scuclk 15>,
> > + <&scuclk 16>,
> > + <&scuclk 17>,
> > + <&scuclk 26>;
> > + reset-names = "fe", "pdma", "qdma", "xsi-mac",
> > + "hsi0-mac", "hsi1-mac", "hsi-mac",
> > + "xfp-mac";
> > +
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > + };
> > --
> > 2.45.2
> >
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