netdev - Re: [PATCH v2 net-next 2/2] net: stmmac: qcom-ethqos: add a DMA-reset quirk for sa8775p-ride

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Message-ID: <CAMRc=MdSte_7MSfR1DAH8fHpHWcOfgPX2SO9DR1UnXrgvMDbdg@mail.gmail.com>
Date: Mon, 1 Jul 2024 22:15:51 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Andrew Lunn <andrew@...n.ch>
Cc: Andrew Halaney <ahalaney@...hat.com>, Vinod Koul <vkoul@...nel.org>, 
	Alexandre Torgue <alexandre.torgue@...s.st.com>, Jose Abreu <joabreu@...opsys.com>, 
	"David S . Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Maxime Coquelin <mcoquelin.stm32@...il.com>, netdev@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, 
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v2 net-next 2/2] net: stmmac: qcom-ethqos: add a DMA-reset
 quirk for sa8775p-ride

On Thu, Jun 27, 2024 at 9:37 PM Andrew Lunn <andrew@...n.ch> wrote:
>
> On Thu, Jun 27, 2024 at 12:07:22PM -0500, Andrew Halaney wrote:
> > On Thu, Jun 27, 2024 at 01:39:47PM GMT, Bartosz Golaszewski wrote:
> > > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> > >
> > > On sa8775p-ride the RX clocks from the AQR115C PHY are not available at
> > > the time of the DMA reset so we need to loop TX clocks to RX and then
> > > disable loopback after link-up. Use the existing callbacks to do it just
> > > for this board.
> > >
> > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> >
> > Sorry, not being very helpful but trying to understand these changes
> > and the general cleanup of stmmac... so I'll point out that I'm still
> > confused by this based on Russell's last response:
> > https://lore.kernel.org/netdev/ZnQLED%2FC3Opeim5q@shell.armlinux.org.uk/
> >
> > Quote:
> >
> >     If you're using true Cisco SGMII, there are _no_ clocks transferred
> >     between the PHY and PCS/MAC. There are two balanced pairs of data
> >     lines and that is all - one for transmit and one for receive. So this
> >     explanation doesn't make sense to me.
> >
>
> Agreed. We need a deeper understanding of the clocking to find an
> acceptable solution to this problem.
>
> Is the MAC extracting a clock from the SERDES lines?
>
> Is the PHY not driving the SERDES lines when there is no link?
>
> For RGMII PHYs, they often do have a clock output at 25 or 50MHz which
> the MAC uses. And some PHY drivers need asking to not turn this clock
> off.  Maybe we need the same here, by asking the PHY to keep the
> SERDES lines running when there is no link?
>

Yes, there are two 50MHz outputs on this PHY but they are not
connected on this board.

> https://elixir.bootlin.com/linux/v6.10-rc5/source/include/linux/phy.h#L781
>
> I also wounder why this is not an issue with plain SGMII, rather than
> overclocked SGMII? Maybe there is already a workaround for SGMII and
> it just needs extended to this not quiet 2500BaseX mode.
>

Well, you pointed out that there is a DMA-reset-related workaround in
place for ethqos so I tried to reuse it in this version. Does it
count? :) We did establish that this mode has no in-band signalling,
so we should be fine with the above solution after all.

Also regarding the PHY mode: on a rather non-technical diagram I
found, the four SGMII signals going to the MAC are referred to as 2.5G
HSGMII, not OCSGMII but I'm not sure if that's just naming convention.

I'm still trying to get more info but it's taking time... :(

Bartosz