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Message-Id: <20240701-b4-dp83869-sfp-v1-3-a71d6d0ad5f8@bootlin.com>
Date: Mon, 01 Jul 2024 10:51:05 +0200
From: Romain Gantois <romain.gantois@...tlin.com>
To: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, 
 Russell King <linux@...linux.org.uk>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, netdev@...r.kernel.org, 
 linux-kernel@...r.kernel.org, Romain Gantois <romain.gantois@...tlin.com>
Subject: [PATCH net-next 3/6] net: phy: dp83869: Ensure that the
 FORCE_LINK_GOOD bit is cleared

This bit is located in the PHY_CONTROL register and should be cleared on
reset. However, this is not always the case, which can cause unexpected
behavior such as link up being incorrectly reported as good when the
DP83869 is brought up directly in RGMII-SGMII bridge mode.

Make sure that this bit is cleared for all operational modes.

Signed-off-by: Romain Gantois <romain.gantois@...tlin.com>
---
 drivers/net/phy/dp83869.c | 29 +++++++++--------------------
 1 file changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 6bb9bb1c0e962..579cf6f84e030 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -713,17 +713,20 @@ static int dp83869_configure_mode(struct phy_device *phydev,
 	if (ret)
 		return ret;
 
-	phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
+	/* The FORCE_LINK_GOOD bit 10 in the PHYCTRL register should be
+	 * unset after a hardware reset but it is not. make sure it is
+	 * cleared so that the PHY can function properly.
+	 * Also configure TX/RX FIFO depth for modes that require it.
+	 */
+	ret = phy_write(phydev, MII_DP83869_PHYCTRL,
+			dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
 			dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
 			DP83869_PHY_CTRL_DEFAULT);
+	if (ret)
+		return ret;
 
 	switch (dp83869->mode) {
 	case DP83869_RGMII_COPPER_ETHERNET:
-		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
-				phy_ctrl_val);
-		if (ret)
-			return ret;
-
 		ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 		if (ret)
 			return ret;
@@ -746,28 +749,14 @@ static int dp83869_configure_mode(struct phy_device *phydev,
 
 		break;
 	case DP83869_1000M_MEDIA_CONVERT:
-		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
-				phy_ctrl_val);
-		if (ret)
-			return ret;
-
 		ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 				    DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 		if (ret)
 			return ret;
 		break;
 	case DP83869_100M_MEDIA_CONVERT:
-		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
-				phy_ctrl_val);
-		if (ret)
-			return ret;
 		break;
 	case DP83869_SGMII_COPPER_ETHERNET:
-		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
-				phy_ctrl_val);
-		if (ret)
-			return ret;
-
 		ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 		if (ret)
 			return ret;

-- 
2.45.2


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