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Message-ID: <juzkq4to4e7mxol5rqh3sx3kd4vhmjvtjamdcbeeothuvogmhu@na3zltibi77w>
Date: Thu, 18 Jul 2024 14:42:07 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Yanteng Si <siyanteng@...ngson.cn>
Cc: andrew@...n.ch, hkallweit1@...il.com, peppe.cavallaro@...com, 
	alexandre.torgue@...s.st.com, joabreu@...opsys.com, Jose.Abreu@...opsys.com, 
	chenhuacai@...nel.org, linux@...linux.org.uk, guyinggang@...ngson.cn, 
	netdev@...r.kernel.org, chris.chenfeiyang@...il.com, si.yanteng@...ux.dev
Subject: Re: [PATCH net-next v14 08/14] net: stmmac: dwmac-loongson: Init ref
 and PTP clocks rate

On Tue, Jul 09, 2024 at 05:37:01PM +0800, Yanteng Si wrote:
> Reference and PTP clocks rate of the Loongson GMAC devices is 125MHz.
> (So is in the GNET devices which support is about to be added.) Set
> the respective plat_stmmacenet_data field up in accordance with that
> so to have the coalesce command and timestamping work correctly.
> 
> Signed-off-by: Feiyang Chen <chenfeiyang@...ngson.cn>
> Signed-off-by: Yinggang Gu <guyinggang@...ngson.cn>
> Signed-off-by: Yanteng Si <siyanteng@...ngson.cn>

Note the maintainers may wish to get a clarification whether the patch
should be qualified as a fix and backported to the stable kernels. In
the later case the Fixes tag should be added with the commit hash
causing the problem.

Anyway. From my perspective the patch looks good. Thanks.

Reviewed-by: Serge Semin <fancer.lancer@...il.com>

-Serge(y)

> ---
>  drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> index 9b2e4bdf7cc7..327275b28dc2 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
> @@ -35,6 +35,9 @@ static void loongson_default_data(struct plat_stmmacenet_data *plat)
>  	/* Disable RX queues routing by default */
>  	plat->rx_queues_cfg[0].pkt_route = 0x0;
>  
> +	plat->clk_ref_rate = 125000000;
> +	plat->clk_ptp_rate = 125000000;
> +
>  	/* Default to phy auto-detection */
>  	plat->phy_addr = -1;
>  
> -- 
> 2.31.4
> 

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