netdev - Re: [PATCH V3 00/10] PCIe TPH and cache direct injection support

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Message-ID: <6b8e2001-7f4a-40aa-a760-a4c709675fb6@davidwei.uk>
Date: Sat, 20 Jul 2024 12:25:21 -0700
From: David Wei <dw@...idwei.uk>
To: Wei Huang <wei.huang2@....com>, linux-pci@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
 netdev@...r.kernel.org
Cc: Jonathan.Cameron@...wei.com, helgaas@...nel.org, corbet@....net,
 davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
 pabeni@...hat.com, alex.williamson@...hat.com, gospo@...adcom.com,
 michael.chan@...adcom.com, ajit.khaparde@...adcom.com,
 somnath.kotur@...adcom.com, andrew.gospodarek@...adcom.com,
 manoj.panicker2@....com, Eric.VanTassell@....com, vadim.fedorenko@...ux.dev,
 horms@...nel.org, bagasdotme@...il.com, bhelgaas@...gle.com
Subject: Re: [PATCH V3 00/10] PCIe TPH and cache direct injection support

On 2024-07-17 13:55, Wei Huang wrote:
> Hi All,
> 
> TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to
> provide optimization hints for requests that target memory space. These hints,
> in a format called steering tag (ST), are provided in the requester's TLP
> headers and allow the system hardware, including the Root Complex, to
> optimize the utilization of platform resources for the requests.
> 
> Upcoming AMD hardware implement a new Cache Injection feature that leverages
> TPH. Cache Injection allows PCIe endpoints to inject I/O Coherent DMA writes
> directly into an L2 within the CCX (core complex) closest to the CPU core that
> will consume it. This technology is aimed at applications requiring high
> performance and low latency, such as networking and storage applications.

This sounds very exciting Wei and it's good to see bnxt support. When
you say 'upcoming AMD hardware' are you able to share exactly which? I
would like to try this out.