lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <dc93865e-e772-422f-92bd-a6d2b96e5d8f@amd.com>
Date: Wed, 24 Jul 2024 08:30:03 -0700
From: Brett Creeley <bcreeley@....com>
To: Kurt Kanzenbach <kurt@...utronix.de>,
 Jesse Brandeburg <jesse.brandeburg@...el.com>,
 Tony Nguyen <anthony.l.nguyen@...el.com>
Cc: "David S. Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>,
 Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
 Maciej Fijalkowski <maciej.fijalkowski@...el.com>,
 Vinicius Costa Gomes <vinicius.gomes@...el.com>,
 intel-wired-lan@...ts.osuosl.org, netdev@...r.kernel.org
Subject: Re: [PATCH iwl-next v2] igc: Get rid of spurious interrupts

On 7/24/2024 12:26 AM, Kurt Kanzenbach wrote:
> On Tue Jul 23 2024, Brett Creeley wrote:
>>> @@ -5811,11 +5815,29 @@ static void igc_watchdog_task(struct work_struct *work)
>>>           if (adapter->flags & IGC_FLAG_HAS_MSIX) {
>>>                   u32 eics = 0;
>>>
>>> -               for (i = 0; i < adapter->num_q_vectors; i++)
>>> -                       eics |= adapter->q_vector[i]->eims_value;
>>> -               wr32(IGC_EICS, eics);
>>> +               for (i = 0; i < adapter->num_q_vectors; i++) {
>>> +                       struct igc_q_vector *q_vector = adapter->q_vector[i];
>>> +                       struct igc_ring *rx_ring;
>>> +
>>> +                       if (!q_vector->rx.ring)
>>> +                               continue;
>>> +
>>> +                       rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index];
>>> +
>>> +                       if (test_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) {
>>> +                               eics |= q_vector->eims_value;
>>> +                               clear_bit(IGC_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags);
>>> +                       }
>>
>> Tiny nit, but is there a reason to not use test_and_clear_bit() here?
> 
> I believe that question was answered by Sebastian on v1:
> 
>   https://lore.kernel.org/all/20240613062426.Om5bQpR3@linutronix.de/
> 
> Other than that no particular reason.

Okay, that makes sense. I should have looked through the previous 
comments. Thanks for the link though.

Thanks,

Brett
> 
> Thanks,
> Kurt

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ