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Message-ID: <ZqyXE0XJkn+Of6rR@shell.armlinux.org.uk>
Date: Fri, 2 Aug 2024 09:21:39 +0100
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: jitendra.vegiraju@...adcom.com
Cc: netdev@...r.kernel.org, alexandre.torgue@...s.st.com,
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Subject: Re: [PATCH net-next v3 1/3] net: stmmac: Add basic dwxgmac4 support
to stmmac core
On Thu, Aug 01, 2024 at 08:18:20PM -0700, jitendra.vegiraju@...adcom.com wrote:
> +static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel)
> +{
> + u32 reg_val = 0;
> + u32 val = 0;
val is unnecessary.
> +
> + reg_val |= mode << XGMAC4_MSEL_SHIFT & XGMAC4_MODE_SELECT;
Consider using:
reg_val |= FIELD_PREP(XGMAC4_MODE_SELECT, mode);
and similarly everywhere else you use a shift and mask. With this, you
can remove _all_ _SHIFT definitions in your header file.
> + reg_val |= channel << XGMAC4_AOFF_SHIFT & XGMAC4_ADDR_OFFSET;
> + reg_val |= XGMAC4_CMD_TYPE | XGMAC4_OB;
> + writel(reg_val, ioaddr + XGMAC4_DMA_CH_IND_CONTROL);
> + val = readl(ioaddr + XGMAC4_DMA_CH_IND_DATA);
> + return val;
return readl(ioaddr + XGMAC4_DMA_CH_IND_DATA);
...
> +void dwxgmac4_dma_init(void __iomem *ioaddr,
> + struct stmmac_dma_cfg *dma_cfg, int atds)
> +{
> + u32 value;
> + u32 i;
> +
> + value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +
> + if (dma_cfg->aal)
> + value |= XGMAC_AAL;
> +
> + if (dma_cfg->eame)
> + value |= XGMAC_EAME;
What if dma_cfg doesn't have these bits set? Is it possible they will be
set in the register?
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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