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Message-Id: <E1sZpoW-000eHZ-0d@rmk-PC.armlinux.org.uk>
Date: Fri, 02 Aug 2024 11:47:12 +0100
From: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To: Serge Semin <fancer.lancer@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Alexei Starovoitov <ast@...nel.org>,
Andrew Halaney <ahalaney@...hat.com>,
bpf@...r.kernel.org,
Daniel Borkmann <daniel@...earbox.net>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Jesper Dangaard Brouer <hawk@...nel.org>,
John Fastabend <john.fastabend@...il.com>,
Jose Abreu <joabreu@...opsys.com>,
linux-arm-kernel@...ts.infradead.org,
linux-arm-msm@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>,
Vinod Koul <vkoul@...nel.org>
Subject: [PATCH net-next 09/14] net: stmmac: dwmac4: move PCS interrupt
control
Control the PCS interrupt mask from the phylink pcs_enable() and
pcs_disable() methods rather than relying on driver variables.
This assumes that GMAC_INT_RGSMIIS, GMAC_INT_PCS_LINK and
GMAC_INT_PCS_ANE are all relevant to the PCS.
Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 30 ++++++++++++++++---
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index ec8e94ddf948..0d261709bee6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -56,9 +56,6 @@ static void dwmac4_core_init(struct mac_device_info *hw,
/* Enable GMAC interrupts */
value = GMAC_INT_DEFAULT_ENABLE;
- if (hw->pcs)
- value |= GMAC_PCS_IRQ_DEFAULT;
-
/* Enable FPE interrupt */
if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
value |= GMAC_INT_FPE_EN;
@@ -759,6 +756,30 @@ static void dwmac4_ctrl_ane(struct stmmac_priv *priv, bool ane, bool srgmi_ral,
dwmac_ctrl_ane(priv->ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
}
+static int dwmac4_mii_pcs_enable(struct phylink_pcs *pcs)
+{
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ void __iomem *ioaddr = spcs->priv->hw->pcsr;
+ u32 intr_enable;
+
+ intr_enable = readl(ioaddr + GMAC_INT_EN);
+ intr_enable |= GMAC_PCS_IRQ_DEFAULT;
+ writel(intr_enable, ioaddr + GMAC_INT_EN);
+
+ return 0;
+}
+
+static void dwmac4_mii_pcs_disable(struct phylink_pcs *pcs)
+{
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ void __iomem *ioaddr = spcs->priv->hw->pcsr;
+ u32 intr_enable;
+
+ intr_enable = readl(ioaddr + GMAC_INT_EN);
+ intr_enable &= ~GMAC_PCS_IRQ_DEFAULT;
+ writel(intr_enable, ioaddr + GMAC_INT_EN);
+}
+
static void dwmac4_mii_pcs_get_state(struct phylink_pcs *pcs,
struct phylink_link_state *state)
{
@@ -772,11 +793,12 @@ static void dwmac4_mii_pcs_get_state(struct phylink_pcs *pcs,
}
static const struct phylink_pcs_ops dwmac4_mii_pcs_ops = {
+ .pcs_enable = dwmac4_mii_pcs_enable,
+ .pcs_disable = dwmac4_mii_pcs_disable,
.pcs_config = dwmac_pcs_config,
.pcs_get_state = dwmac4_mii_pcs_get_state,
};
-
static struct phylink_pcs *
dwmac4_phylink_select_pcs(struct stmmac_priv *priv, phy_interface_t interface)
{
--
2.30.2
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