netdev - Re: [PATCH net-next v26 07/13] rtase: Implement a function to receive packets

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Message-ID: <20240808200705.0e77147c@kernel.org>
Date: Thu, 8 Aug 2024 20:07:05 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: Justin Lai <justinlai0215@...ltek.com>
Cc: <davem@...emloft.net>, <edumazet@...gle.com>, <pabeni@...hat.com>,
 <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>, <andrew@...n.ch>,
 <jiri@...nulli.us>, <horms@...nel.org>, <rkannoth@...vell.com>,
 <jdamato@...tly.com>, <pkshih@...ltek.com>, <larry.chiu@...ltek.com>
Subject: Re: [PATCH net-next v26 07/13] rtase: Implement a function to
 receive packets

On Wed, 7 Aug 2024 11:37:17 +0800 Justin Lai wrote:
> +static int rx_handler(struct rtase_ring *ring, int budget)
> +{
> +	union rtase_rx_desc *desc_base = ring->desc;
> +	u32 pkt_size, cur_rx, delta, entry, status;
> +	struct rtase_private *tp = ring->ivec->tp;
> +	struct net_device *dev = tp->dev;
> +	union rtase_rx_desc *desc;
> +	struct sk_buff *skb;
> +	int workdone = 0;
> +
> +	cur_rx = ring->cur_idx;
> +	entry = cur_rx % RTASE_NUM_DESC;
> +	desc = &desc_base[entry];
> +
> +	do {
> +		/* make sure discriptor has been updated */
> +		dma_rmb();

I think I already asked, but this still makes no sense to me.
dma barriers are between accesses to descriptors.
dma_rmb() ensures ordering of two reads.
Because modern CPUs can perform reads out of order.
What two reads is this barrier ordering?

Please read the doc on memory barriers relating to dma.
I think this is in the wrong place.

r8169 gets it right.

> +		status = le32_to_cpu(desc->desc_status.opts1);
> +
> +		if (status & RTASE_DESC_OWN)
> +			break;
> +