| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240812134816.380688-4-Parthiban.Veerasooran@microchip.com>
Date: Mon, 12 Aug 2024 19:18:12 +0530
From: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com>
To: <andrew@...n.ch>, <hkallweit1@...il.com>, <linux@...linux.org.uk>,
<davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <ramon.nordin.rodriguez@...roamp.se>
CC: <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<parthiban.veerasooran@...rochip.com>, <UNGLinuxDriver@...rochip.com>,
<Thorsten.Kummermehr@...rochip.com>, Parthiban Veerasooran
<Parthiban.Veerasooran@...rochip.com>
Subject: [PATCH net-next 3/7] net: phy: microchip_t1s: add support for Microchip's LAN865X Rev.B1
This patch adds support for LAN8650/1 Rev.B1. As per the latest
configuration note AN1760 released (Revision F (DS60001760G - June 2024))
for Rev.B0 is also applicable for Rev.B1. Refer hardware revisions list
in the latest AN1760.
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com>
---
drivers/net/phy/Kconfig | 4 +--
drivers/net/phy/microchip_t1s.c | 62 ++++++++++++++++-----------------
2 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 7fddc8306d82..68db15d52355 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -282,8 +282,8 @@ config MICREL_PHY
config MICROCHIP_T1S_PHY
tristate "Microchip 10BASE-T1S Ethernet PHYs"
help
- Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0 Internal
- PHYs.
+ Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1
+ Internal PHYs.
config MICROCHIP_PHY
tristate "Microchip PHYs"
diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c
index 51ff97ffad0e..187540ae95c0 100644
--- a/drivers/net/phy/microchip_t1s.c
+++ b/drivers/net/phy/microchip_t1s.c
@@ -4,7 +4,7 @@
*
* Support: Microchip Phys:
* lan8670/1/2 Rev.B1
- * lan8650/1 Rev.B0 Internal PHYs
+ * lan8650/1 Rev.B0/B1 Internal PHYs
*/
#include <linux/kernel.h>
@@ -12,7 +12,8 @@
#include <linux/phy.h>
#define PHY_ID_LAN867X_REVB1 0x0007C162
-#define PHY_ID_LAN865X_REVB0 0x0007C1B3
+/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */
+#define PHY_ID_LAN865X_REVB 0x0007C1B3
#define LAN867X_REG_STS2 0x0019
@@ -59,12 +60,12 @@ static const u16 lan867x_revb1_fixup_masks[12] = {
0x0600, 0x7F00, 0x2000, 0xFFFF,
};
-/* LAN865x Rev.B0 configuration parameters from AN1760
+/* LAN865x Rev.B0/B1 configuration parameters from AN1760
* As per the Configuration Application Note AN1760 published in the below link,
* https://www.microchip.com/en-us/application-notes/an1760
* Revision F (DS60001760G - June 2024)
*/
-static const u32 lan865x_revb0_fixup_registers[17] = {
+static const u32 lan865x_revb_fixup_registers[17] = {
0x00D0, 0x00E0, 0x00E9, 0x00F5,
0x00F4, 0x00F8, 0x00F9, 0x0081,
0x0091, 0x0043, 0x0044, 0x0045,
@@ -72,7 +73,7 @@ static const u32 lan865x_revb0_fixup_registers[17] = {
0x0050,
};
-static const u16 lan865x_revb0_fixup_values[17] = {
+static const u16 lan865x_revb_fixup_values[17] = {
0x3F31, 0xC000, 0x9E50, 0x1CF8,
0xC020, 0xB900, 0x4E53, 0x0080,
0x9660, 0x00FF, 0xFFFF, 0x0000,
@@ -80,23 +81,23 @@ static const u16 lan865x_revb0_fixup_values[17] = {
0x0002,
};
-static const u16 lan865x_revb0_fixup_cfg_regs[2] = {
+static const u16 lan865x_revb_fixup_cfg_regs[2] = {
0x0084, 0x008A,
};
-static const u32 lan865x_revb0_sqi_fixup_regs[12] = {
+static const u32 lan865x_revb_sqi_fixup_regs[12] = {
0x00B0, 0x00B1, 0x00B2, 0x00B3,
0x00B4, 0x00B5, 0x00B6, 0x00B7,
0x00B8, 0x00B9, 0x00BA, 0x00BB,
};
-static const u16 lan865x_revb0_sqi_fixup_values[12] = {
+static const u16 lan865x_revb_sqi_fixup_values[12] = {
0x0103, 0x0910, 0x1D26, 0x002A,
0x0103, 0x070D, 0x1720, 0x0027,
0x0509, 0x0E13, 0x1C25, 0x002B,
};
-static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = {
+static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] = {
0x00AD, 0x00AE, 0x00AF,
};
@@ -108,7 +109,7 @@ static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = {
*
* 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2
*/
-static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr)
+static int lan865x_revb_indirect_read(struct phy_device *phydev, u16 addr)
{
int ret;
@@ -134,7 +135,7 @@ static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offsets[])
int ret;
for (int i = 0; i < ARRAY_SIZE(fixup_regs); i++) {
- ret = lan865x_revb0_indirect_read(phydev, fixup_regs[i]);
+ ret = lan865x_revb_indirect_read(phydev, fixup_regs[i]);
if (ret < 0)
return ret;
@@ -183,11 +184,11 @@ static int lan865x_write_cfg_params(struct phy_device *phydev,
static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[])
{
- u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)];
- u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)];
+ u16 cfg_results[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];
+ u16 cfg_params[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)];
int ret;
- ret = lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs,
+ ret = lan865x_read_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,
cfg_params, ARRAY_SIZE(cfg_params));
if (ret)
return ret;
@@ -197,17 +198,17 @@ static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[])
0x03;
cfg_results[1] = FIELD_PREP(GENMASK(15, 10), (40 + offsets[1]) & 0x3F);
- return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs,
+ return lan865x_write_cfg_params(phydev, lan865x_revb_fixup_cfg_regs,
cfg_results, ARRAY_SIZE(cfg_results));
}
static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[])
{
- u16 cfg_results[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)];
- u16 cfg_params[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)];
+ u16 cfg_results[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];
+ u16 cfg_params[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)];
int ret;
- ret = lan865x_read_cfg_params(phydev, lan865x_revb0_sqi_fixup_cfg_regs,
+ ret = lan865x_read_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,
cfg_params, ARRAY_SIZE(cfg_params));
if (ret)
return ret;
@@ -219,12 +220,11 @@ static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offsets[])
cfg_results[2] = FIELD_PREP(GENMASK(15, 8), (17 + offsets[0]) & 0x3F) |
((22 + offsets[0]) & 0x3F);
- return lan865x_write_cfg_params(phydev,
- lan865x_revb0_sqi_fixup_cfg_regs,
+ return lan865x_write_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs,
cfg_results, ARRAY_SIZE(cfg_results));
}
-static int lan865x_revb0_config_init(struct phy_device *phydev)
+static int lan865x_revb_config_init(struct phy_device *phydev)
{
s8 offsets[2];
int ret;
@@ -236,10 +236,10 @@ static int lan865x_revb0_config_init(struct phy_device *phydev)
if (ret)
return ret;
- for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) {
+ for (int i = 0; i < ARRAY_SIZE(lan865x_revb_fixup_registers); i++) {
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
- lan865x_revb0_fixup_registers[i],
- lan865x_revb0_fixup_values[i]);
+ lan865x_revb_fixup_registers[i],
+ lan865x_revb_fixup_values[i]);
if (ret)
return ret;
@@ -254,10 +254,10 @@ static int lan865x_revb0_config_init(struct phy_device *phydev)
if (ret)
return ret;
- for (int i = 0; i < ARRAY_SIZE(lan865x_revb0_sqi_fixup_regs); i++) {
+ for (int i = 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) {
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
- lan865x_revb0_sqi_fixup_regs[i],
- lan865x_revb0_sqi_fixup_values[i]);
+ lan865x_revb_sqi_fixup_regs[i],
+ lan865x_revb_sqi_fixup_values[i]);
if (ret)
return ret;
}
@@ -332,10 +332,10 @@ static struct phy_driver microchip_t1s_driver[] = {
.get_plca_status = genphy_c45_plca_get_status,
},
{
- PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0),
- .name = "LAN865X Rev.B0 Internal Phy",
+ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB),
+ .name = "LAN865X Rev.B0/B1 Internal Phy",
.features = PHY_BASIC_T1S_P2MP_FEATURES,
- .config_init = lan865x_revb0_config_init,
+ .config_init = lan865x_revb_config_init,
.read_status = lan86xx_read_status,
.get_plca_cfg = genphy_c45_plca_get_cfg,
.set_plca_cfg = genphy_c45_plca_set_cfg,
@@ -347,7 +347,7 @@ module_phy_driver(microchip_t1s_driver);
static struct mdio_device_id __maybe_unused tbl[] = {
{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },
- { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) },
+ { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) },
{ }
};
--
2.34.1
Powered by blists - more mailing lists