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Message-ID: <7fba32da-09b7-e9d8-c859-b01f073d127e@amd.com>
Date: Mon, 19 Aug 2024 12:13:54 +0100
From: Alejandro Lucero Palau <alucerop@....com>
To: Zhi Wang <zhiw@...dia.com>
Cc: alejandro.lucero-palau@....com, linux-cxl@...r.kernel.org,
netdev@...r.kernel.org, dan.j.williams@...el.com, martin.habets@...inx.com,
edward.cree@....com, davem@...emloft.net, kuba@...nel.org,
pabeni@...hat.com, edumazet@...gle.com, richard.hughes@....com,
targupta@...dia.com, zhiwang@...nel.org
Subject: Re: [PATCH v2 01/15] cxl: add type2 device basic support
On 8/17/24 21:32, Zhi Wang wrote:
> On Mon, 12 Aug 2024 12:34:55 +0100
> Alejandro Lucero Palau <alucerop@....com> wrote:
>
>> On 8/9/24 09:34, Zhi Wang wrote:
>>> On Mon, 15 Jul 2024 18:28:21 +0100
>>> <alejandro.lucero-palau@....com> wrote:
>>>
>>>> From: Alejandro Lucero <alucerop@....com>
>>>>
>>>> Differientiate Type3, aka memory expanders, from Type2, aka device
>>>> accelerators, with a new function for initializing cxl_dev_state.
>>>>
>>>> Create opaque struct to be used by accelerators relying on new
>>>> access functions in following patches.
>>>>
>>>> Add SFC ethernet network driver as the client.
>>>>
>>>> Based on
>>>> https://lore.kernel.org/linux-cxl/168592149709.1948938.8663425987110396027.stgit@dwillia2-xfh.jf.intel.com/T/#m52543f85d0e41ff7b3063fdb9caa7e845b446d0e
>>>>
>>>> Signed-off-by: Alejandro Lucero <alucerop@....com>
>>>> Co-developed-by: Dan Williams <dan.j.williams@...el.com>
>>>> ---
>>>> drivers/cxl/core/memdev.c | 52
>>>> ++++++++++++++++++++++++++ drivers/net/ethernet/sfc/Makefile |
>>>> 2 +- drivers/net/ethernet/sfc/efx.c | 4 ++
>>>> drivers/net/ethernet/sfc/efx_cxl.c | 53
>>>> +++++++++++++++++++++++++++ drivers/net/ethernet/sfc/efx_cxl.h |
>>>> 29 +++++++++++++++ drivers/net/ethernet/sfc/net_driver.h | 4 ++
>>>> include/linux/cxl_accel_mem.h | 22 +++++++++++
>>>> include/linux/cxl_accel_pci.h | 23 ++++++++++++
>>>> 8 files changed, 188 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/net/ethernet/sfc/efx_cxl.c
>>>> create mode 100644 drivers/net/ethernet/sfc/efx_cxl.h
>>>> create mode 100644 include/linux/cxl_accel_mem.h
>>>> create mode 100644 include/linux/cxl_accel_pci.h
>>>>
>>>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>>>> index 0277726afd04..61b5d35b49e7 100644
>>>> --- a/drivers/cxl/core/memdev.c
>>>> +++ b/drivers/cxl/core/memdev.c
>>>> @@ -8,6 +8,7 @@
>>>> #include <linux/idr.h>
>>>> #include <linux/pci.h>
>>>> #include <cxlmem.h>
>>>> +#include <linux/cxl_accel_mem.h>
>>> Let's keep the header inclusion in an alphabetical order. The same
>>> in efx_cxl.c
>>
>> The headers seem to follow a reverse Christmas tree order here rather
>> than an alphabetical one.
>>
>> Should I rearrange them all?
>>
> Let's fix them.
>
I'll do.
Thanks!
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