netdev - Re: [net PATCH v3] octeontx2-af: Fix CPT AF register offset calculation

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Message-ID: <20240821150050.GB2164@kernel.org>
Date: Wed, 21 Aug 2024 16:00:50 +0100
From: Simon Horman <horms@...nel.org>
To: Bharat Bhushan <bbhushan2@...vell.com>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	sgoutham@...vell.com, gakula@...vell.com, sbhatta@...vell.com,
	hkelam@...vell.com, davem@...emloft.net, edumazet@...gle.com,
	kuba@...nel.org, pabeni@...hat.com, jerinj@...vell.com,
	lcherian@...vell.com, ndabilpuram@...vell.com
Subject: Re: [net PATCH v3] octeontx2-af: Fix CPT AF register offset
 calculation

On Wed, Aug 21, 2024 at 12:35:58PM +0530, Bharat Bhushan wrote:
> Some CPT AF registers are per LF and others are global. Translation
> of PF/VF local LF slot number to actual LF slot number is required
> only for accessing perf LF registers. CPT AF global registers access
> do not require any LF slot number. Also, there is no reason CPT
> PF/VF to know actual lf's register offset.
> 
> Without this fix microcode loading will fail, VFs cannot be created
> and hardware is not usable.
> 
> Fixes: bc35e28af789 ("octeontx2-af: replace cpt slot with lf id on reg write")
> Signed-off-by: Bharat Bhushan <bbhushan2@...vell.com>
> ---
> v3:
>   - Updated patch description about what's broken without this fix
>   - Added patch history
> 
> v2: https://lore.kernel.org/netdev/20240819152744.GA543198@kernel.org/T/
>   - Spelling fixes in patch description
> 
> v1: https://lore.kernel.org/lkml/CAAeCc_nJtR2ryzoaXop8-bbw_0RGciZsniiUqS+NVMg7dHahiQ@mail.gmail.com/T/
>   - Added "net" in patch subject prefix, missed in previous patch:
>     https://lore.kernel.org/lkml/20240806070239.1541623-1-bbhushan2@marvell.com/
> 

Thanks for the updates, and the information below the scissors ('---').

Reviewed-by: Simon Horman <horms@...nel.org>