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Message-ID: <CAKxU2N8j5Fw1spACmNyWniKGpSWtMt0H3KY5JZj5zYaA0c69kA@mail.gmail.com>
Date: Thu, 29 Aug 2024 10:47:01 -0700
From: Rosen Penev <rosenp@...il.com>
To: Simon Horman <horms@...nel.org>
Cc: netdev@...r.kernel.org, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, linux@...linux.org.uk,
linux-kernel@...r.kernel.org, o.rempel@...gutronix.de, p.zabel@...gutronix.de
Subject: Re: [PATCHv2 net-next] net: ag71xx: update FIFO bits and descriptions
On Thu, Aug 29, 2024 at 9:52 AM Simon Horman <horms@...nel.org> wrote:
>
> On Wed, Aug 28, 2024 at 03:38:47PM -0700, Rosen Penev wrote:
> > Taken from QCA SDK. No functional difference as same bits get applied.
> >
> > Signed-off-by: Rosen Penev <rosenp@...il.com>
> > ---
> > v2: forgot to send to netdev
> > drivers/net/ethernet/atheros/ag71xx.c | 48 +++++++++++++--------------
> > 1 file changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
> > index db2a8ade6205..692dbded8211 100644
> > --- a/drivers/net/ethernet/atheros/ag71xx.c
> > +++ b/drivers/net/ethernet/atheros/ag71xx.c
> > @@ -149,11 +149,11 @@
> > #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
> > #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
> > #define FIFO_CFG4_DR BIT(10) /* Dribble */
> > -#define FIFO_CFG4_LE BIT(11) /* Long Event */
> > -#define FIFO_CFG4_CF BIT(12) /* Control Frame */
> > -#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
> > -#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
> > -#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
> > +#define FIFO_CFG4_CF BIT(11) /* Control Frame */
> > +#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
> > +#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
> > +#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
> > +#define FIFO_CFG4_LE BIT(15) /* Long Event */
> > #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
> > #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
> > #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
> > @@ -168,28 +168,28 @@
> > #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
> > #define FIFO_CFG5_FC BIT(2) /* False Carrier */
> > #define FIFO_CFG5_CE BIT(3) /* Code Error */
> > -#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
> > -#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
> > -#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
> > -#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
> > -#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
> > -#define FIFO_CFG5_DR BIT(9) /* Dribble */
> > -#define FIFO_CFG5_CF BIT(10) /* Control Frame */
> > -#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
> > -#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
> > -#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
> > -#define FIFO_CFG5_LE BIT(14) /* Long Event */
> > -#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
> > -#define FIFO_CFG5_16 BIT(16) /* unknown */
> > -#define FIFO_CFG5_17 BIT(17) /* unknown */
> > +#define FIFO_CFG5_CR BIT(4) /* CRC error */
> > +#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
> > +#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
> > +#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
> > +#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
> > +#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
> > +#define FIFO_CFG5_DR BIT(10) /* Dribble */
> > +#define FIFO_CFG5_CF BIT(11) /* Control Frame */
> > +#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
> > +#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
> > +#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
> > +#define FIFO_CFG5_LE BIT(15) /* Long Event */
> > +#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
> > +#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
> > #define FIFO_CFG5_SF BIT(18) /* Short Frame */
> > #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
> > #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
> > - FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
> > - FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
> > - FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
> > - FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
> > - FIFO_CFG5_17 | FIFO_CFG5_SF)
> > + FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_L0 | \
>
> FIFO_CFG5_LO
>
> > + FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
> > + FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
> > + FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
> > + FIFO_CFG5_UC | FIFO_CFG5_SF)
> >
> > #define AG71XX_REG_TX_CTRL 0x0180
> > #define TX_CTRL_TXE BIT(0) /* Tx Enable */
>
> Please consider a patch to allow compilation of this driver with
> COMPILE_TEST in order to increase build coverage.
Is that just
--- a/drivers/net/ethernet/atheros/Kconfig
+++ b/drivers/net/ethernet/atheros/Kconfig
@@ -6,7 +6,7 @@
config NET_VENDOR_ATHEROS
bool "Atheros devices"
default y
- depends on (PCI || ATH79)
+ depends on (PCI || ATH79 || COMPILE_TEST)
help
If you have a network (Ethernet) card belonging to this class, say Y.
@@ -19,7 +19,7 @@ if NET_VENDOR_ATHEROS
config AG71XX
tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
- depends on ATH79
+ depends on ATH79 || COMPILE_TEST
select PHYLINK
imply NET_SELFTESTS
help
>
> --
> pw-bot: cr
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