netdev - Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

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Message-ID: <100f9c30-f6cc-4995-a6e9-2856dd3a029f@lunn.ch>
Date: Thu, 12 Sep 2024 18:13:15 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Ronnie.Kunin@...rochip.com
Cc: Raju.Lakkaraju@...rochip.com, netdev@...r.kernel.org,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, Bryan.Whitehead@...rochip.com,
	UNGLinuxDriver@...rochip.com, linux@...linux.org.uk,
	maxime.chevallier@...tlin.com, rdunlap@...radead.org,
	Steen.Hegelund@...rochip.com, Daniel.Machon@...rochip.com,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

> Our PCI11x1x hardware has a single MDIO controller that gets used
> regardless of whether the chip interface is set to RGMII or to
> SGMII/BASE-X.

That would be the external MDIO bus. 

But where is the PCS connected?

> When we are using an SFP, the MDIO lines from our controller are not
> used / connected at all to the SFP.

Correct. The SFP cage does not have MDIO pins. There are two commonly
used protocols for MDIO over I2C, which phylink supports. The MAC
driver is not involved. All it needs to report to phylink is when the
PCS transitions up/down.

    Andrew