netdev - RE: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

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Message-ID:
 <PH8PR11MB79651E0A10963CD805666D9295642@PH8PR11MB7965.namprd11.prod.outlook.com>
Date: Thu, 12 Sep 2024 18:51:40 +0000
From: <Ronnie.Kunin@...rochip.com>
To: <andrew@...n.ch>
CC: <Raju.Lakkaraju@...rochip.com>, <netdev@...r.kernel.org>,
	<davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
	<pabeni@...hat.com>, <Bryan.Whitehead@...rochip.com>,
	<UNGLinuxDriver@...rochip.com>, <linux@...linux.org.uk>,
	<maxime.chevallier@...tlin.com>, <rdunlap@...radead.org>,
	<Steen.Hegelund@...rochip.com>, <Daniel.Machon@...rochip.com>,
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs



> -----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Thursday, September 12, 2024 12:13 PM
> To: Ronnie Kunin - C21729 <Ronnie.Kunin@...rochip.com>
> Cc: Raju Lakkaraju - I30499 <Raju.Lakkaraju@...rochip.com>; netdev@...r.kernel.org;
> davem@...emloft.net; edumazet@...gle.com; kuba@...nel.org; pabeni@...hat.com; Bryan
> Whitehead - C21958 <Bryan.Whitehead@...rochip.com>; UNGLinuxDriver
> <UNGLinuxDriver@...rochip.com>; linux@...linux.org.uk; maxime.chevallier@...tlin.com;
> rdunlap@...radead.org; Steen Hegelund - M31857 <Steen.Hegelund@...rochip.com>; Daniel Machon -
> M70577 <Daniel.Machon@...rochip.com>; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> > Our PCI11x1x hardware has a single MDIO controller that gets used
> > regardless of whether the chip interface is set to RGMII or to
> > SGMII/BASE-X.
> 
> That would be the external MDIO bus.
> 
> But where is the PCS connected?

For SGMII/BASE-X support the PCI11010 uses Synopsys IP which is all internal to the device. The registers of this Synopsys block are accessible indirectly using a couple of registers (called SGMII_ACCESS and SGMII_DATA) that are mapped into the PCI11010 PCIe BAR.

> 
> > When we are using an SFP, the MDIO lines from our controller are not
> > used / connected at all to the SFP.
> 
> Correct. The SFP cage does not have MDIO pins. There are two commonly used protocols for MDIO over
> I2C, which phylink supports. The MAC driver is not involved. All it needs to report to phylink is when the
> PCS transitions up/down.
> 
>     Andrew