netdev - [PATCH 2/5] net: phy: dp83tg720: Added SGMII Support

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Message-ID: <dcb62e7332fae6ca41e55a7698a7011adada6d86.1726263095.git.a-reyes1@ti.com>
Date: Thu, 19 Sep 2024 14:01:16 -0700
From: "Alvaro (Al-vuh-roe) Reyes" <a-reyes1@...com>
To: <netdev@...r.kernel.org>
CC: <andrew@...n.ch>, <hkallweit1@...il.com>, <linux@...linux.org.uk>,
        <maxime.chevallier@...tlin.com>, <o.rempel@...gutronix.de>,
        <spatton@...com>, <r-kommineni@...com>, <e-mayhew@...com>,
        <praneeth@...com>, <p-varis@...com>, <d-qiu@...com>,
        "Alvaro (Al-vuh-roe) Reyes" <a-reyes1@...com>
Subject: [PATCH 2/5] net: phy: dp83tg720: Added SGMII Support

Adding SGMII Support to driver by checking if SGMII is enabled and
writing to the SGMII registers to ensure PHY is configured correctly.


Signed-off-by: Alvaro (Al-vuh-roe) Reyes <a-reyes1@...com>
---
 drivers/net/phy/dp83tg720.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c
index 7e81800cfc5b..a6f90293aa61 100644
--- a/drivers/net/phy/dp83tg720.c
+++ b/drivers/net/phy/dp83tg720.c
@@ -12,6 +12,9 @@
 
 #define DP83TG720_PHY_ID			0x2000a284
 
+#define MMD1F							0x1f
+#define MMD1							0x1
+
 /* MDIO_MMD_VEND2 registers */
 #define DP83TG720_MII_REG_10			0x10
 #define DP83TG720_STS_MII_INT			BIT(7)
@@ -69,6 +72,13 @@
 
 #define DP83TG720_SQI_MAX			7
 
+/* SGMII CTRL Registers/bits */
+#define DP83TG720_SGMII_CTRL			0x0608
+#define SGMII_CONFIG_VAL				0x027B
+#define DP83TG720_SGMII_AUTO_NEG_EN		BIT(0)
+#define DP83TG720_SGMII_EN				BIT(9)
+
+
 /**
  * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY.
  * @phydev: Pointer to the phy_device structure.
@@ -306,7 +316,7 @@ static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)
 
 static int dp83tg720_config_init(struct phy_device *phydev)
 {
-	int ret;
+	int value, ret;
 
 	/* Software Restart is not enough to recover from a link failure.
 	 * Using Hardware Reset instead.
@@ -327,6 +337,19 @@ static int dp83tg720_config_init(struct phy_device *phydev)
 			return ret;
 	}
 
+	value = phy_read_mmd(phydev, MMD1F, DP83TG720_SGMII_CTRL);
+	if (value < 0)
+		return value;
+
+	if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
+		value |= DP83TG720_SGMII_EN;
+	else
+		value &= ~DP83TG720_SGMII_EN;
+
+	ret = phy_write_mmd(phydev, MMD1F, DP83TG720_SGMII_CTRL, value);
+	if (ret < 0)
+		return ret;
+
 	/* In case the PHY is bootstrapped in managed mode, we need to
 	 * wake it.
 	 */
-- 
2.17.1