netdev - Re: [RFC PATCH] net: dsa: mv88e6xxx: correct CC scale factor for 88E6393X

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Message-ID: <890714d7-bc6a-45b2-854b-d1b431f8a0eb@shenghaoyang.info>
Date: Sun, 22 Sep 2024 19:15:47 +0800
From: Shenghao Yang <me@...nghaoyang.info>
To: Andrew Lunn <andrew@...n.ch>
Cc: netdev@...r.kernel.org, f.fainelli@...il.com, olteanv@...il.com,
 pavana.sharma@...i.com, ashkan.boldaji@...i.com, kabel@...nel.org
Subject: Re: [RFC PATCH] net: dsa: mv88e6xxx: correct CC scale factor for
 88E6393X

On 16/9/24 03:14, Andrew Lunn wrote:
> On Sun, Sep 15, 2024 at 07:57:27PM +0800, Shenghao Yang wrote:
>> Sending this as an RFC: no datasheet access - this
>> scaling factor may not be correct for all boards if this
>> 4ns vs 8ns discrepancy is down to physical design.
>>
>> If the counter is truly spec'd to always count at
>> 250MHz other chips in the same family may need
>> correction too.
> 
> This sort of text should be placed below the --- marker so it is not
> part of the commit message which actually get merged.

Hi Andrew,

Gotcha - I'll move things around in the future.

> There is a register MV88E6XXX_TAI_CLOCK_PERIOD which indicates the
> period of one clock tick. It probably defaults to 0x0FA0, or 4000
> decimal which should be correct for the internal clock. But if an
> external clock is being used, it needs to be set to 0x1F40, or 8000
> decimal. It would be good if you could read it out and see if it is
> correct by default.

Thanks! The register appears to contain the correct value on this
device - 4000ps using the 250MHz internal clock.

Would you happen to know if that register is valid for all the
families currently supported? 

I'm preparing a few patches to read off that register in 
mv88e6xxx_ptp_setup() and choose a correct set of cycle counter
coefficients to avoid introducing more device-specific handling.

If that sounds reasonable I'll send them for net - would you also be
okay with a Suggested-By?

Shenghao