netdev - [PATCH v2 4/4] riscv: dts: starfive: jh7110: Add CAN nodes

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Message-ID: <20240922145151.130999-5-hal.feng@starfivetech.com>
Date: Sun, 22 Sep 2024 22:51:50 +0800
From: Hal Feng <hal.feng@...rfivetech.com>
To: Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Marc Kleine-Budde <mkl@...gutronix.de>,
	Vincent Mailhol <mailhol.vincent@...adoo.fr>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Albert Ou <aou@...s.berkeley.edu>
Cc: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
	William Qiu <william.qiu@...rfivetech.com>,
	Hal Feng <hal.feng@...rfivetech.com>,
	devicetree@...r.kernel.org,
	linux-can@...r.kernel.org,
	netdev@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v2 4/4] riscv: dts: starfive: jh7110: Add CAN nodes

From: William Qiu <william.qiu@...rfivetech.com>

Add can0/1 support for StarFive JH7110 SoC.

Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 32 ++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0d8339357bad..368cc40829f9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -929,6 +929,38 @@ watchdog@...70000 {
 				 <&syscrg JH7110_SYSRST_WDT_CORE>;
 		};
 
+		can0: can@...d0000 {
+			compatible = "starfive,jh7110-can", "cast,can-ctrl-fd-7x10N00S00";
+			reg = <0x0 0x130d0000 0x0 0x1000>;
+			interrupts = <112>;
+			clocks = <&syscrg JH7110_SYSCLK_CAN0_APB>,
+				 <&syscrg JH7110_SYSCLK_CAN0_TIMER>,
+				 <&syscrg JH7110_SYSCLK_CAN0_CAN>;
+			clock-names = "apb", "timer", "core";
+			resets = <&syscrg JH7110_SYSRST_CAN0_APB>,
+				 <&syscrg JH7110_SYSRST_CAN0_TIMER>,
+				 <&syscrg JH7110_SYSRST_CAN0_CORE>;
+			reset-names = "apb", "timer", "core";
+			starfive,syscon = <&sys_syscon 0x10 0x3 0x8>;
+			status = "disabled";
+		};
+
+		can1: can@...e0000 {
+			compatible = "starfive,jh7110-can", "cast,can-ctrl-fd-7x10N00S00";
+			reg = <0x0 0x130e0000 0x0 0x1000>;
+			interrupts = <113>;
+			clocks = <&syscrg JH7110_SYSCLK_CAN1_APB>,
+				 <&syscrg JH7110_SYSCLK_CAN1_TIMER>,
+				 <&syscrg JH7110_SYSCLK_CAN1_CAN>;
+			clock-names = "apb", "timer", "core";
+			resets = <&syscrg JH7110_SYSRST_CAN1_APB>,
+				 <&syscrg JH7110_SYSRST_CAN1_TIMER>,
+				 <&syscrg JH7110_SYSRST_CAN1_CORE>;
+			reset-names = "apb", "timer", "core";
+			starfive,syscon = <&sys_syscon 0x88 0x12 0x40000>;
+			status = "disabled";
+		};
+
 		crypto: crypto@...00000 {
 			compatible = "starfive,jh7110-crypto";
 			reg = <0x0 0x16000000 0x0 0x4000>;
-- 
2.43.2