[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <1727726138-2203615-1-git-send-email-radhey.shyam.pandey@amd.com>
Date: Tue, 1 Oct 2024 01:25:35 +0530
From: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
To: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <michal.simek@....com>, <radhey.shyam.pandey@....com>,
<abin.joseph@....com>, <u.kleine-koenig@...gutronix.de>,
<elfring@...rs.sourceforge.net>, <harini.katakam@....com>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<git@....com>
Subject: [PATCH net-next 0/3] net: xilinx: emaclite: Adopt clock support
This patchset adds emaclite clock support. AXI Ethernet Lite IP can also
be used on SoC platforms like Zynq UltraScale+ MPSoC which combines
powerful processing system (PS) and user-programmable logic (PL) into
the same device. On these platforms it is mandatory to explicitly enable
IP clocks for proper functionality.
Abin Joseph (3):
dt-bindings: net: emaclite: Add clock support
net: emaclite: Replace alloc_etherdev() with devm_alloc_etherdev()
net: emaclite: Adopt clock support
.../bindings/net/xlnx,emaclite.yaml | 3 +++
drivers/net/ethernet/xilinx/xilinx_emaclite.c | 22 ++++++++++---------
2 files changed, 15 insertions(+), 10 deletions(-)
base-commit: c824deb1a89755f70156b5cdaf569fca80698719
--
2.34.1
Powered by blists - more mailing lists