netdev - RE: [Intel-wired-lan] [PATCH v12 iwl-next 7/7] ice: Implement PTP support for E830 devices

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Message-ID: <CYYPR11MB842919C5C3BAE3EE4751DCC1BD722@CYYPR11MB8429.namprd11.prod.outlook.com>
Date: Fri, 4 Oct 2024 15:04:43 +0000
From: "Pucha, HimasekharX Reddy" <himasekharx.reddy.pucha@...el.com>
To: "Kolacinski, Karol" <karol.kolacinski@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "Greenwalt, Paul" <paul.greenwalt@...el.com>, Michal Michalik
	<michal.michalik@...el.com>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, Frederic Weisbecker <frederic@...nel.org>,
	"Kolacinski, Karol" <karol.kolacinski@...el.com>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "Keller, Jacob E" <jacob.e.keller@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>, Anna-Maria Behnsen
	<anna-maria@...utronix.de>, "Olech, Milena" <milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH v12 iwl-next 7/7] ice: Implement PTP
 support for E830 devices

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Karol Kolacinski
> Sent: Monday, September 30, 2024 5:43 PM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: Greenwalt, Paul <paul.greenwalt@...el.com>; Michal Michalik <michal.michalik@...el.com>; netdev@...r.kernel.org; Frederic Weisbecker <frederic@...nel.org>; Kolacinski, Karol <karol.kolacinski@...el.com>; Nguyen, Anthony L <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@...el.com>; Keller, Jacob E <jacob.e.keller@...el.com>; Thomas Gleixner <tglx@...utronix.de>; Anna-Maria Behnsen <anna-maria@...utronix.de>; Olech, Milena <milena.olech@...el.com>
> Subject: [Intel-wired-lan] [PATCH v12 iwl-next 7/7] ice: Implement PTP support for E830 devices
>
> From: Michal Michalik <michal.michalik@...el.com>
>
> Add specific functions and definitions for E830 devices to enable PTP support.
>
> E830 devices support direct write to GLTSYN_ registers without shadow registers and 64 bit read of PHC time.
>
> Enable PTM for E830 device, which is required for cross timestamp and and dependency on PCIE_PTM for ICE_HWTS.
>
> Check X86_FEATURE_ART for E830 as it may not be present in the CPU.
>
> Cc: Anna-Maria Behnsen <anna-maria@...utronix.de>
> Cc: Frederic Weisbecker <frederic@...nel.org>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@...el.com>
> Co-developed-by: Jacob Keller <jacob.e.keller@...el.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@...el.com>
> Co-developed-by: Milena Olech <milena.olech@...el.com>
> Signed-off-by: Milena Olech <milena.olech@...el.com>
> Co-developed-by: Paul Greenwalt <paul.greenwalt@...el.com>
> Signed-off-by: Paul Greenwalt <paul.greenwalt@...el.com>
> Signed-off-by: Michal Michalik <michal.michalik@...el.com>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@...el.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@...el.com>
> ---
> V11 -> V12: Fixed missing E830 case in ice_get_base_incval()
> V10 -> V11: Fixed adjustments not working on E830
> V9 -> V10: Removed ICE_FLAG_PTP_SUPPORTED check for E830, which was disabling
>            PTP only for E830
> V7 -> V8: Moved E830 parts of other patches to this patch
> V6 -> V7: Fixed timestamp acquisition
> V4 -> V5: Edited return values
> V3 -> V4: Fixed kdoc for other ice_is_e***() and other _e830() functions in
>           ice_ptp_hw.c
> V2 -> V3: Fixed kdoc for ice_is_e***() and ice_ptp_init_phy_e830()
> V1 -> V2: Fixed compilation issue with GENMASK bits higher than 32
>
>  drivers/net/ethernet/intel/Kconfig            |   2 +-
>  .../net/ethernet/intel/ice/ice_hw_autogen.h   |  12 ++
>  drivers/net/ethernet/intel/ice/ice_main.c     |   9 +-
>  drivers/net/ethernet/intel/ice/ice_ptp.c      |  71 +++++++-
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c   | 167 +++++++++++++++++-
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h   |   8 +
>  6 files changed, 262 insertions(+), 7 deletions(-)
>

Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@...el.com> (A Contingent worker at Intel)